Home > Community > Tags > IBM
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *


  • 32 nm Test Chips Show Layout 'Context' Matters

    Real silicon reveals a lot about how new silicon processes work, and two 32 nm test chips that Cadence recently completed on Common Platform high-k metal gate (HKMG) technology were particularly helpful from a modeling perspective. One conclusion: when you get to 32 nm and below, the “context”...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 8 2009
  • Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

    Does the union of verification automation and IT+source code management tools get you all misty eyed? If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have you gushing tears of joy. Specifically, this video...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, Aug 27 2009
  • Re: Assura QRC extraction problem

    Any news on this issue. I have the same problem with and IBM kit from MOIS. Basically the varactors are defaulting to their PCELL length once they have been extracted (IC 5.1.41_USR5 / Assura 3.1.7 / QRC(EXT) 7.1.2). Also the tech file will not load in the QRC form. This is not the case for DRC and LVS...
    Posted to Custom IC Design (Forum) by Toyrunner on Tue, Jun 2 2009
  • DRC problems with IBM PDK

    Hello, I have access to the IBM PDKs for both 65nm (cmos10lpe) and 45nm (soi120S). I wanted to test the PDK and the DRC tool so I made a layout containing just one nmos and ran DRC on it. To my surprise, I got DRC errors for the IBM PDK nmos cell using the IBM PDK DRC runset. Shouldn't the cell provided...
    Posted to Digital Implementation (Forum) by weiz on Thu, May 28 2009
  • ARM libraries, IBM PDK, Cadence PVS questions...

    Hi all, I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS. Sorry if I posted in the wrong place ARM Libraries 1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool IBK PDK 1. After I installed it, I got the following warning message in Virtuoso CIW...
    Posted to Custom IC Design (Forum) by weiz on Wed, Apr 29 2009
  • Functional Coverage for Embedded Software

    Hardware verification has evolved into keeping track of a pile of different types of coverage. There is line coverage, expression coverage, toggle coverage, assertion coverage, finite state machine coverage, and functional coverage. There are probably more types I'm forgetting related to low power...
    Posted to System Design and Verification (Weblog) by jasona on Fri, Jan 9 2009
  • Hug a Money Tree

    If you watch TV here in the U.S., you've probably seen at least one of the commercials from IBM for their "go green" campaign. There is a story thread that spans a few of these, here is part of it: (if you can't see the above video, it's at http://www.youtube.com/watch?v=VSNFE6eUjfY...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Nov 14 2008
  • OVM - The "O" Means Opportunity

    A few months back I blogged that OVM was " Open for Business ". A nice play on words, if I do say so myself, but is there real opportunity now that the door is open? 5200 OVM World participants. 10,000 downloads. 2100 forum posts. 200+ LinkedIn OVM Professionals. That certainly describes an...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Fri, Oct 31 2008
  • The cell world

    Earlier this Summer, I was lucky enough to attend the CDNLive show in Japan. One of the keynote speakers at the show was Mr. Mitsuo Saito, Chief Fellow at Toshiba Corporation Semiconductor Company. Mr. Saito-san delivered a presentation about the 20 years battle for the fastest application-specific processors...
    Posted to System Design and Verification (Weblog) by Ran Avinun on Wed, Sep 24 2008
Page 5 of 5 (49 items) < Previous 1 2 3 4 5