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IBM

Guest Blog: Characterizing Process Variability At 32 nm And Below

Process characterization becomes much more complex as feature sizes shrink. In this guest blog Jim Bordelon, president and CTO of Stratosphere Solutions , describes requirements and methodologies for modeling variability at 32 nm and below. Peering under the hood of a 32 nm process early in its lifecycle...

Posted to Industry Insights (Weblog) by rgoering on Wed, Nov 18 2009
Panelists: 32 nm HKMG Is Ready To Roll

The 32/28 nm Common Platform high-k metal gate (HKMG) technology is “ready and open for business,” according to the title of a breakfast panel at the ARM Techcon3 conference Oct. 22. Panelists from IBM , ARM and Cadence talked about the benefits of HKMG, the requirements it places on the...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 28 2009
Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

Last week Cadence’s new CMO John Bruggeman extended a personal invitation to all of you to join us for CDNLive San Jose 2009 . With 60+ papers, tutorials, and workshops, live and webcasted, we’re expecting even bigger attendance than back in 2007 (our biggest ever). Those of you attending...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Sat, Oct 3 2009
Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

I'm not proud to admit that I reacted with envy to the news that Twitter just received a $1 billion valuation . This story inspired further chatter claiming that if Twitter plays their cards right, they could achieve a $5 billion valuation before long. That's right: this fresh new internet combination...

Posted to Functional Verification (Weblog) by jvh3 on Wed, Sep 23 2009
32 nm Test Chips Show Layout 'Context' Matters

Real silicon reveals a lot about how new silicon processes work, and two 32 nm test chips that Cadence recently completed on Common Platform high-k metal gate (HKMG) technology were particularly helpful from a modeling perspective. One conclusion: when you get to 32 nm and below, the “context”...

Posted to Industry Insights (Weblog) by rgoering on Tue, Sep 8 2009
Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Does the union of verification automation and IT+source code management tools get you all misty eyed? If so, this wedding video of the "Enterprise Verification Management Solution" (taken in the IBM booth at DAC 2009 by yours truly) will have you gushing tears of joy. Specifically, this video...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Aug 27 2009
Re: Assura QRC extraction problem

Any news on this issue. I have the same problem with and IBM kit from MOIS. Basically the varactors are defaulting to their PCELL length once they have been extracted (IC 5.1.41_USR5 / Assura 3.1.7 / QRC(EXT) 7.1.2). Also the tech file will not load in the QRC form. This is not the case for DRC and LVS...

Posted to Custom IC Design (Forum) by Toyrunner on Tue, Jun 2 2009
DRC problems with IBM PDK

Hello, I have access to the IBM PDKs for both 65nm (cmos10lpe) and 45nm (soi120S). I wanted to test the PDK and the DRC tool so I made a layout containing just one nmos and ran DRC on it. To my surprise, I got DRC errors for the IBM PDK nmos cell using the IBM PDK DRC runset. Shouldn't the cell provided...

Posted to Digital Implementation (Forum) by weiz on Thu, May 28 2009
ARM libraries, IBM PDK, Cadence PVS questions...

Hi all, I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS. Sorry if I posted in the wrong place ARM Libraries 1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool IBK PDK 1. After I installed it, I got the following warning message in Virtuoso CIW...

Posted to Custom IC Design (Forum) by weiz on Wed, Apr 29 2009
Functional Coverage for Embedded Software

Hardware verification has evolved into keeping track of a pile of different types of coverage. There is line coverage, expression coverage, toggle coverage, assertion coverage, finite state machine coverage, and functional coverage. There are probably more types I'm forgetting related to low power...

Posted to System Design and Verification (Weblog) by jasona on Fri, Jan 9 2009

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IBM

Guest Blog: Characterizing Process Variability At 32 nm And Below

Panelists: 32 nm HKMG Is Ready To Roll

Skeptical That TLM D&V Makes Designers More Productive? Come and See for Yourself!

Twitter-like Growth For Verification's Trailblazers? (a/k/a A Trailblazer hat tip to new CMO John B.)

32 nm Test Chips Show Layout 'Context' Matters

Wedding at DAC '09: CDNS+IBM's Enterprise Verification Management Solution

Re: Assura QRC extraction problem

DRC problems with IBM PDK

ARM libraries, IBM PDK, Cadence PVS questions...

Functional Coverage for Embedded Software