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IBM

Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements

No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 9 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 1 2012
On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

The Common Platform Technology Forum held March 14 in Santa Clara, California, provided an updated look at process technology, design challenges, and ecosystem collaboration at 28nm and below. Much of the content is available throughout 2012 as part of a Virtual Technology Forum . Following is a report...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 19 2012
Video: Easing the Design Challenges of Double Patterning at 20nm

Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...

Posted to Industry Insights (Weblog) by rgoering on Tue, Aug 23 2011
Layout of Enclosed Gate Transistors (EGTs or ELTs)

Hello, I'm designing an enclosed layout transistor but can not pass both DRC and LVS. I'm running IBM's PDK cmrf7sf V1.8.0.6 ML, out of virtuoso rev 6.1.4, and my simulator is Assura. Does anyone have any experience in getting a ELT to pass DRC and LVS in this process? Any help would be greatly...

Posted to Custom IC Design (Forum) by bnugent on Wed, Jun 15 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation

A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 14 2011
Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM Platform

Circuits implemented using sub-micron technologies require designers to meet tighter and tighter specifications despite increasing statistical variation and complexity. High correlations between actual silicon and circuit verification using advanced SPICE models are therefore a must to ensure first pass...

Posted to Custom IC Design (Weblog) by helenet on Wed, Feb 23 2011
Power Modeling Standards Effort Aims to Ease IP Integration

A new standards effort that could ease low-power silicon IP integration is quietly underway at the Silicon Integration Initiative (Si2) Low Power Coalition ( LPC ). Although the LPC is probably best known as the home of the Common Power Format (CPF) originated by Cadence, it actually has a much broader...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 26 2011
Panel: Is the Cloud the Solution to IC Design Collaboration?

Semiconductor design increasingly requires collaboration by geographically-dispersed design teams, as well as partners and third-party suppliers. Private or public cloud computing may provide a rich environment for this collaboration, but some key questions and challenges remain, according to panelists...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jan 20 2011
Common Platform Forum: A Clearer Path to Advanced Process Nodes

Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jan 18 2011

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IBM

Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements

CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning

On-Line Presentation: 20nm Design Challenges, and a Look Ahead to 14nm

Video: Easing the Design Challenges of Double Patterning at 20nm

Layout of Enclosed Gate Transistors (EGTs or ELTs)

DAC Panel Calls Off “Battle” Between Prototyping and Emulation

Q&A: IBM Modeling Team Describes Advanced SOI Qualification Flow In Cadence MMSIM Platform

Power Modeling Standards Effort Aims to Ease IP Integration

Panel: Is the Cloud the Solution to IC Design Collaboration?

Common Platform Forum: A Clearer Path to Advanced Process Nodes