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High-level Synthesis,System Design and Verification
abstraction
Acceleration
Alex Kondratyev
ARM
ASIC
ASIC/ASSP
C to Silicon
C++
Cadence
Calypto
CDNLive
CDNLive!
CircuitSutra
clock gating
CoFluent
control
control-dominated
Co-verification
C-to-Silcon
C-to-Silicon 12.2
C-to-Silicon Compiler
DATE
EDA360
EDN
ESL
Fast Models
Flex Channels
FPGA
Freescale
high level synthesis
hls
Imperas
IP
IP assembly
IP re-use
ip-xact
Jack Erickson
Jeda
Low-Power
Magillem
MDV
metric-driven verification
modeling
Models
QoR
Registers
RTL
RTL Compiler
SoC
synthesis
system
system design
System Design and Verifcation
System Realization
SystemC
SystemC TLM2
system-level
TLM
TLM 2.0
TLM 2.0-driven design
TLM2
TLM-driven design
transaction level modeling
TSMC
Virtual Platforms
virtual prototype
virtual protoype
virual platform
XtremeEDA
What to See at the DATE Conference: High-Level Synthesis
The DATE (Design Automation and Test in Europe) Conference is next week (March 18-22, 2013) in Grenoble, France. If you are lucky enough to be in Grenoble at this time of year, it will be worth it to check out Session 11.2 "High-Level Synthesis and Coarse-Grained Reconfigurable Architectures."...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Mar 14 2013
C-to-Silicon 12.2 Available for Your Holiday Shopping List
The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 13 2012
High Level Synthesis for a Control-Dominated Design?
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 15 2011
IP Cannot be an Efficient Abstraction Level Without SystemC!
EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Fri, Aug 12 2011
De-Mystifying SystemC: What is TLM?
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Feb 3 2011
SystemC: It's Neither Complicated Nor Belligerent!
I was recently talking to a customer who was looking to move up in abstraction from RTL to SystemC for all the usual good reasons (increased verification productivity, broader micro-architecture exploration, easier re-use, etc). However he was concerned that the learning curve for his team would be too...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Jan 24 2011
System Realization Webinars in 2010 -- A Summary
Last year was unprecedented for Cadence. We came up with the EDA360 vision , reorganized internally to align to that vision, and established some great partnerships to help our customers realize their own visions around EDA360. The ED360 vision paper has been well received by both customers and competition...
Posted to
System Design and Verification
(Weblog)
by
MayankBhatia
on Fri, Jan 7 2011
System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)
2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Thu, Dec 16 2010
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