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Differentiation Through Hardware is Not Going Away
Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Mar 5 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design
Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jan 22 2012
TLM: The Year in Review, and Trends for 2012
2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Jan 2 2012
High Level Synthesis for a Control-Dominated Design?
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 15 2011
How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?
During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Nov 22 2011
17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?
In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts came to my mind: Wow! What is their ROI of migrating...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Oct 4 2011
IP Cannot be an Efficient Abstraction Level Without SystemC!
EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Fri, Aug 12 2011
Q&A: Linking Virtual Prototypes to High-Level Synthesis
Virtual prototypes for early software development and high-level synthesis tools for hardware implementation are two important new technologies that are raising the abstraction level in electronic systems design. But these tools are traditionally isolated from one another because they require different...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 29 2011
IEEE SystemC Standard Revision – Here’s What to Expect
Standards are living, evolving entities, and SystemC -- standardized in 2005 as IEEE 1666 -- is no exception. This language, which has become indispensable for virtual platforms, high-level synthesis, and transaction-level modeling (TLM) design and verification, is undergoing a new revision this year...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 9 2011
De-Mystifying SystemC: What is TLM?
In my last post I briefly mentioned that when designing hardware with SystemC, you do not need to allocate logic to register boundaries. And I said that was a blog post for another day. The first step is to separate the core functionality of the block from the way it interfaces to the system. So if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Feb 3 2011
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