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High-Level Synthesis,C-to-Silicon Compiler

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part II)

2010 was a very dynamic year for the electronic systems industry overall and Cadence in particular. In this set of blogs, I discuss some of the trends that started in 2010 and will continue in 2011. In part I, I talked about the key growth market, key industry challenges and the role of EDA. In this...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Dec 28 2010
System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry...

Posted to System Design and Verification (Weblog) by Ran Avinun on Thu, Dec 16 2010
Methodology Is Important But Language Matters - Part 2

In this blog, I would like to discuss the direction in the languages that will be chosen for TLM (or ESL) verification. Transaction-Level Models have been used for long time as simulation models. As we start to use more and more high-level synthesis, the link to design and implementation is becoming...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Feb 9 2010
CtoS support of Multiple Clocks

In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support multiple threads in a similar way that traditional Hardware Description Languages (HDLs) support multiple processes. There are many applications, such as multi-rate DSP applications, in which it is not only necessary...

Posted to System Design and Verification (Weblog) by TeamESL on Mon, Apr 20 2009
C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis tool. The question is usually based on the fact that SystemC is the input language for CtoS. It is partially correct. In reality, CtoS is both a High and a Low level synthesis tool. On the High Level side...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, Apr 3 2009
C-to-Silicon Does Not Require a Library Characterization

One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis tools is its ability to directly read industry standards .lib files. By providing this ability an expensive library characterization which is required by other ESL Synthesis tools is avoided. This approach not only avoids...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, Feb 13 2009
New Blog series- Team ESL

Cadence is well known for its leadership in system verification leveraging its HW-assisted verification market segment. Last year, we have expanded this segment offering, combined it with our System Software capabilities (focusing on Electronic System Level - ESL) into a larger segment - System Design...

Posted to System Design and Verification (Weblog) by Ran Avinun on Fri, Feb 13 2009

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High-Level Synthesis,C-to-Silicon Compiler

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part II)

System Industry Trends - 2010 Highlights and What's Coming Up for 2011 (Part 1)

Methodology Is Important But Language Matters - Part 2

CtoS support of Multiple Clocks

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

C-to-Silicon Does Not Require a Library Characterization

New Blog series- Team ESL