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The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis?
The electronics industry has enjoyed constant growth while undergoing constant transformation. One of the most significant transformations has been the source of that growth -- from the PC revolution, to the rise of the internet, to mobile computing. The consensus is that the next growth driver is going...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, May 14 2013
What to See at the DATE Conference: High-Level Synthesis
The DATE (Design Automation and Test in Europe) Conference is next week (March 18-22, 2013) in Grenoble, France. If you are lucky enough to be in Grenoble at this time of year, it will be worth it to check out Session 11.2 "High-Level Synthesis and Coarse-Grained Reconfigurable Architectures."...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Mar 14 2013
University of Aizu and Cadence Collaborate to Deliver a Course Featuring High-Level Synthesis
Today we issued a Japan-only press release announcing a high-level synthesis joint development program with the University of Aizu. This is Japan's first university-level course teaching high-level synthesis for semiconductor design. Here is the link to the full release, and if you can't read...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, Dec 17 2012
C-to-Silicon 12.2 Available for Your Holiday Shopping List
The winter holiday season is that special time of year when we get bombarded with catalogs, emails, television commercials, banner ads, store displays, and any other method to get our attention on something that somebody is trying to sell. Having been trained as an engineer, I'm able to filter a...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 13 2012
CDNLive paper: High-level Synthesis on Video Processing ASIC
The proceedings from the recent CDNLive! event in Israel recently became available, and you can access them with your Cadence.com account login. The paper entitled "High-level Synthesis on Video Processing ASIC" delivered by Yaniv Fais and Michael Zarubinsky of Freescale gives a great look...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Nov 14 2012
Margins are Costly - Don't Let Them Grow Out of Control!
Last week, Professor Jan Rabaey of the University of California at Berkeley gave a great keynote at Cadence's Low Power Technology Summit that called for changes to the conventional solutions for power reduction. One of the points he made was that today's designs are over-designed and over-constrained...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Oct 24 2012
Si2 Talk: Why System-Level Low Power is Challenging
There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative ( Si2 ) Conference. "What's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 15 2012
Q&A: Phil Bishop, New Cadence VP, Drives Adoption of System-Level Design
Phil Bishop has come into his new role - Vice President and General Manager of System Level Design at Cadence - at an exciting time. After years of slow growth, technologies such as high-level synthesis and virtual prototyping are seeing adoption and showing results in more and more production environments...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Oct 8 2012
iPhone5 Differentiation is Chip Design
In case you may have missed it, Apple recently launched a new iPhone. As per the iPhone launch tradition, it brings with it a lot of excitement over the latest capabilities. Of course we don't know everything until it is actually available, but this latest incarnation has broken all kinds of records...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Wed, Sep 19 2012
C-to-Silicon Japan User Group and Ikegami Production Experience
We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, information, and ideas so that we can all benefit. We...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Tue, Jul 3 2012
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