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High-Level Synthesis

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 25 2012
System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
Is System Modeling the Next EDA Abstraction Level?

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 15 2012
Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design," which Richard Goering summarizes very well in his blog post "Will Differentiation Through Software Kill Chip Design?" The short answer is that hardware design is not going away, but that the costs...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Mar 5 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design

Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 22 2012
TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 2 2012
Synthesis User Panel: Power Dominates Front End Design

What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list. The panel included three user presenters, an ARM executive, and a Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 19 2011
High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 15 2011
How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

During the planning phase for SoC designs, teams have to choose whether to "make or buy" the pieces of IP that will compose the SoC. The drivers of this decision are well-chronicled in a recent article by Ann Steffora Mutchler, appropriately titled "Make vs. Buy". I won't re-hash...

Posted to System Design and Verification (Weblog) by Jack Erickson on Tue, Nov 22 2011
17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?

In their presentation at the recent SystemC Japan conference, Renesas Micro Systems, Inc. (RMS) stated 2 SystemC "beginners" completed a 17M gate design in 8 months, achieving first-pass timing closure at 650 MHz targeting 40nm. Two thoughts came to my mind: Wow! What is their ROI of migrating...

Posted to System Design and Verification (Weblog) by Jack Erickson on Tue, Oct 4 2011

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High-Level Synthesis

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

System-Level Low Power Design – What Will it Take to Move There?

Is System Modeling the Next EDA Abstraction Level?

Differentiation Through Hardware is Not Going Away

Q&A: Frank Schirrmeister Updates Status of System-Level Design

TLM: The Year in Review, and Trends for 2012

Synthesis User Panel: Power Dominates Front End Design

High Level Synthesis for a Control-Dominated Design?

How Will High-Level Synthesis Affect the Make vs. Buy vs. Re-use Decision?

17M Gates in 8 Months with 2 Designers -- What is Your ROI for Higher-Abstraction Design and Verification?