Home > Community > Tags > HLS

	Login with a Cadence account.
Not a member yet? Create a permanent login account to make interactions with Cadence more conveniennt. Register \| Membership benefits

Get email delivery of the Cadence blog (individual posts).

Popular Tags

Browse All Tags

Email
Social Web

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Send yourself a copy

Cadence RSS Feeds

Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.

Contact Us

Cadence Contacts

Global Office Locator
Find Offices worldwide »

Sales Inquiry
Request for Product information »
Cadence Channel Partners »

Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Send Yourself A Copy

HLS

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

It's that time of the year again! The 49 th Design Automation Conference ( DAC 2012 ) is just a little over one month away, and Cadence will have an active presence on the exhibit floor, on panel discussions, in tutorials and workshops, in the user track, and in a co-located event that includes a...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 25 2012
System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
Is System Modeling the Next EDA Abstraction Level?

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting...

Posted to Industry Insights (Weblog) by rgoering on Sun, Apr 15 2012
Q&A: Frank Schirrmeister Updates Status of System-Level Design

Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, has been managing and marketing system-level design technology for over 15 years. He's a widely published and respected author on the topic, with a monthly blog at the Chip Design Magazine...

Posted to Industry Insights (Weblog) by rgoering on Sun, Jan 22 2012
TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design and verification, after spending my entire career to that point in RTL. I made my move upward in abstraction level in mid-2010 because it seemed like the time had finally come for this methodology to start becoming mainstream...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Jan 2 2012
High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 15 2011
IP Cannot be an Efficient Abstraction Level Without SystemC!

EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...

Posted to System Design and Verification (Weblog) by Jack Erickson on Fri, Aug 12 2011
Q&A: Linking Virtual Prototypes to High-Level Synthesis

Virtual prototypes for early software development and high-level synthesis tools for hardware implementation are two important new technologies that are raising the abstraction level in electronic systems design. But these tools are traditionally isolated from one another because they require different...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 29 2011
Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration in SoCs. Even with IP re-use comprising a large percentage of new SoCs, new IP must also be developed in order to differentiate on the hardware side. With RTL containing so much application-specific implementation...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, May 16 2011
Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over at EE Times entitled "The evolution of design methodology" (part 1) . Their conclusion is that the chip design industry is in the midst of another major shift to one where chip design becomes software-centric...

Posted to System Design and Verification (Weblog) by Jack Erickson on Mon, Nov 29 2010

Page 1 of 3 (24 items) 1 2 3 Next >

Popular Tags

Share

Subscribe

Contact Us

HLS

See Cadence at DAC 2012 – Panels, Tutorials, “I Love DAC,” and the Denali Party

System-Level Low Power Design – What Will it Take to Move There?

Is System Modeling the Next EDA Abstraction Level?

Q&A: Frank Schirrmeister Updates Status of System-Level Design

TLM: The Year in Review, and Trends for 2012

High Level Synthesis for a Control-Dominated Design?

IP Cannot be an Efficient Abstraction Level Without SystemC!

Q&A: Linking Virtual Prototypes to High-Level Synthesis

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Evolution and Synthesis