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HDL

  • Help with editing Schematic Description

    I am trying to create scheatic using Allegro Design Entry HDL (Version 16.5). I am learning this software since 2-3 days and I need help on how to edit the schematic description like <DRAWING_TITLE_HEADER>, <PRODUCT>, etc. (Please find corresponding image attached) I tried going to Tools>Options>Custom...
    Posted to PCB Design (Forum) by abhikuvar on Fri, Apr 18 2014
  • WARNING(SPMHNI-184): Device library warning detected.

    Hi, I encountered the below error, how to solve this? #1 WARNING(SPMHNI-184): Device library warning detected. WARNING(SPMHNI-198): Problems with device 'PIC16F1829-SOIC20,MICROCHIP TEA'. Pinname 'CCP2/P2A/T1CKI/SD02/T1OSI/OSC1/CLKIN/RA5' is replaced by '$0': 'Pin name is...
    Posted to PCB Design (Forum) by maberu on Mon, Mar 3 2014
  • WARNING(SPMHNI-184): Device library warning detected.

    Hi, I encountered below error, how should this be solved? #1 WARNING(SPMHNI-184): Device library warning detected. WARNING(SPMHNI-198): Problems with device 'PIC16F1829-SOIC20,MICROCHIP TEA'. Pinname 'CCP2/P2A/T1CKI/SD02/T1OSI/OSC1/CLKIN/RA5' is replaced by '$0': 'Pin name...
    Posted to Digital Implementation (Forum) by maberu on Mon, Mar 3 2014
  • How to add additional delimiter in BOM - HDL?

    Hi, How can I add additional delimiter in BOM - HDL? The delimiter present in my BOM - HDL are COMMA, SEMICOLON, COLON, SPACE, DOT, HASH # and TAB. But on my colleague's pc, there is no TAB delimiter. How can I add TAB delimiter in his pc? By the way, we are using the same license. Thanks, Mabel
    Posted to PCB Design (Forum) by maberu on Thu, Dec 19 2013
  • Q&A: Phil Moorby, Verilog Inventor and Cadence Fellow, Sees a Parallel Future

    Few people have influenced the EDA industry as much as Phil Moorby, inventor of the Verilog hardware description language (HDL) and the first Verilog simulator. As Cadence celebrates its 25 th anniversary this year, Moorby was a key contributor to that success, both as the developer of Verilog at Gateway...
    Posted to Industry Insights (Weblog) by rgoering on Wed, Dec 4 2013
  • Export Physical not adding pin numbers until component is replaced in ConceptHDL

    I recently ran into a strange issue where Export Physical (with back annotation enabled) was not adding pin numbers to the component symbol in ConceptHDL. However, if I deleted the symbol from the schematc and added it back from the Component Browser, and then ran Export Physical with back annotation...
    Posted to PCB Design (Forum) by chwilso3 on Sun, Sep 8 2013
  • Creating Regions in Cadence Allegro front to back flow

    What is the process for creating a region with unique physical and spacing properties when one is working with the front to back flow? Is one supposed to create the constraint region in the Allegro HDL contraint manager and then have the layout engineer draw the region in the physical board and then...
    Posted to PCB Design (Forum) by FrostbiteFalls on Mon, Aug 19 2013
  • ERROR(SPCODD-563): Following blocks have netlisting errors.

    Hi! I would like to ask what are the possible cause for this error when packaging? ERROR(SPCODD-563): Following blocks have netlisting errors. I can't locate the errors using markers. This was designed in other location and when was sent (through archive in project manager) to me for troubleshooting...
    Posted to PCB Design (Forum) by maberu on Tue, Jul 23 2013
  • Re: Pick and Place include variant changes

    Jürgen, Considering you are using Concept HDL Variant Editor, Variant data can be included and variant list can be exported. With this data you can generate an assembly view as per the variant file. When the assembly view is seen, select all the components attach a unique property to differentiate...
    Posted to PCB Design (Forum) by Ravinsu on Wed, Jul 17 2013
  • Design Lock in HDL / Read-only Design

    Hi, I would like to ask how to make the schematic design a read-only file. All previously created schematic designs will be uploaded in the server. These designs can be used by other design engineers for their projects. Engineers can reuse the existing designs (blocks) but are not allowed to modify or...
    Posted to PCB Design (Forum) by maberu on Thu, Jul 11 2013
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