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Customer, Partner DFM Concerns Spur New Methodologies
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 7 2012
ARM TechCon Address: High Stakes at Low Process Nodes
The complexity of advanced-node IC designs is skyrocketing, and the demands on EDA tool development seem overwhelming - but innovation and deep collaboration will break through the challenges, according to Chi-Ping Hsu, senior vice president for R&D at the Silicon Realization group at Cadence. In...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 25 2011
GLOBALFOUNDRIES DRC+ Donation: New Era for DFM Standards?
DRC+, a pattern-matching design for manufacturability (DFM) technique developed by GLOBALFOUNDRIES in collaboration with Cadence, is heading for standardization through the Silicon Integration Initiative (Si2). As announced Oct. 20 at the Si2 Conference , GLOBALFOUNDRIES has donated DRC+ data structures...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Oct 23 2011
“In Design” DFM Signoff – the Inside Story
As noted in a recent customer announcement with Fujitsu, Cadence offers "in design" design for manufacturability (DFM) signoff for digital, mixed-signal and custom IC design. The basic idea is simple - engineers run signoff DFM checks during the physical design process, instead of waiting until...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Oct 5 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow
The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Sep 7 2011
GTC Panel: Getting Best Use From Older IC Process Nodes
Time for a mainstream revolution? That was the title of a lively panel discussion at the Global Technology Conference ( GTC ) Aug. 30. Panelists noted that there's still a lot of activity at 65nm and above. They discussed why this is true, whether mature nodes can be retrofitted with new capabilities...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Sep 5 2011
GTC Panel: CEOs Navigate a Changing IC Ecosystem
Semiconductor and system design have never been more promising -- or more challenging. How can IC design companies find their way to sucess? At the Global Technology Conference (GTC) Aug. 30, three CEOs and one vice president gave their perspectives on the rapidly changing IC design and manufacturing...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Sep 1 2011
GTC: GLOBALFOUNDRIES Charts Course for 28nm, 20nm and Beyond
The 28nm node is "fully enabled" and ready for production ramp-up, and 20nm early adopter flows are available now, according to GLOBALFOUNDRIES executives at the Global Technology Conference (GTC) in Santa Clara, California Aug. 30. In several morning sessions, speakers updated the company's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 31 2011
Panel Video: Preventing IP Theft in a Global Market
How can semiconductor companies ensure IP integrity in a global marketplace? Are foundries liable if customers use stolen semiconductor IP? Do systems companies really care if their semiconductor IP is stolen? These are some of the questions that emerged at a Design Automation Conference panel in June...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Aug 4 2011
Common Platform Forum: A Clearer Path to Advanced Process Nodes
Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 18 2011
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