Home > Community > Tags > Functional Verification
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Functional Verification

  • Grey-Boxed Data-Path Approach Using 'when sub-typing'

    [Please join Team Specman in welcoming the first guest blogger from our user base: Ms. Kaberi Banerjee, a senior design & verification engineer based in Silicon Valley California] Fellow Specmaniacs (or should I say "specmites" – in alignment with the subject of bugs!), I recently...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Feb 18 2009
  • Adaptive Chips Selects OVM Over VMM -- An Interview With Amjad Qureshi

    On February 11 Cadence announced that Adaptive Chips had adopted the Incisive verification solution using the OVM to improve its verification process. I had the opportunity to "virtually" sit down with Amjad Qureshi, Vice President of Technology at Adaptive Chips, to ask him a few questions...
    Posted to Functional Verification (Weblog) by Adam Sherilog on Wed, Feb 18 2009
  • Post-Show Thoughts on DesignCon 2009

    Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and I'm finally finding a few minutes to comment on the event. I have a soft spot in my heart for this conference; I think that I've presented something in some form at every show but one since it was called Design...
    Posted to Functional Verification (Weblog) by tomacadence on Thu, Feb 12 2009
  • Road Trip!

    As at most companies these days, Cadence is doing what it can to minimize travel expenses wherever possible. Consequently, whereas my business trips used to always involve an airplane in some way, these days myself and my colleagues fan out by car from our repective offices to visit customers. Hence...
    Posted to Functional Verification (Weblog) by jvh3 on Thu, Feb 12 2009
  • Of EDA Vendors and Conferences

    There's an interesting thread on Cool Verification ( http://www.coolverification.com/2009/02/dvcon-misfits-unite.html ) about the number of papers at DVCon 2009 authored or co-authored by EDA vendors. There seems to be an assumption on the part of some posters that vendor involvement implies marketing...
    Posted to Functional Verification (Weblog) by tomacadence on Thu, Feb 5 2009
  • Report From DesignCon 2009

    This week the " DesignCon " show is in town (<= 10 minutes from the Cadence campus at the Santa Clara convention center), so I couldn't resist the opportunity to check out some of the speeches and exhibits. I'm happy to report that my curiosity was rewarded -- here are my notes along...
    Posted to Functional Verification (Weblog) by jvh3 on Tue, Feb 3 2009
  • Good Article Alert: End "EDA Bashing"

    Allow me to direct your attention to a most welcome article in EDA DesignLine written by Gabe Moretti: Title: [End] EDA bashing http://www.edadesignline.com/213000305?cid=RSSfeed_EDAdesignline_edadlALL In a nutshell, the article argues that general, blanket criticism of the EDA industry -- "EDA...
    Posted to Functional Verification (Weblog) by jvh3 on Mon, Feb 2 2009
  • "...Yes, Virginia there is a Specman"

    I usually try to visit many of our customers in Europe (and other parts of the world) at least a couple of times a year. On my last trip in October, while I was in Stockholm, I ended up having beers at a pub with one of our local AEs and a Specman customer. This customer had been telling me about all...
    Posted to Functional Verification (Weblog) by mstellfox on Mon, Feb 2 2009
  • Interview With Cadence Verification IP Architect Levent Caglar

    Even in these challenging economic times, interest in Verification IP ("VIP") has remained very strong. To learn more about the issues and concerns around the "make vs. buy" decision that comes with any IP product, I hosted the following interview with VIP expert Levent Caglar. Enjoy...
    Posted to Functional Verification (Weblog) by jvh3 on Mon, Feb 2 2009
  • Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

    While simulating a VHDL design with Incisive Simulator, if an integer overflow is detected, the simulation stops with the following error message: Error! integer overflow File: ./test.vhd, line = 13, pos = 11 Scope: :$PROCESS_000 Time: 10 FS + 0 ./test.vhd:13 i := i - 1; Incisive is probably the only...
    Posted to Functional Verification (Weblog) by adua on Wed, Jan 28 2009
Page 47 of 52 (516 items) « First ... < Previous 45 46 47 48 49 Next > ... Last »