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Functional Verification,debug,verification
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Develop for Debugability – Part 1
Debugging is the most time-critical activity of any verification engineer. Finding a bug is very often a combination of having a good hunch, experience, and the quality of testbench code that you need to analyze. Since having a good hunch and experience is something everyone needs to acquire for themselves...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Apr 8 2013
DVCon 2013 for the Specmaniac
At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects of our verification technologies and methodologies (full list of Cadence-sponsored events is here ). Of course, Team Specman cannot resist drawing your attention to the many activities that will feature Specman and...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Thu, Feb 7 2013
DVCon 2013 Preview – Learn from Other Design and Verification Engineers
The Design and Verification Conference ( DVCon 2013 ) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 24 2013
Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck
Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 29 2012
My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!
The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation problem that you might face. The most obvious and common generation problem is a contradiction, but the Gen Debugger can handle various other problems, such as user errors, performance problems and unexpected generation...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Apr 24 2012
User View: Why and How to Use Transaction-Based Acceleration
Transaction-based acceleration can speed up simulation hundreds of times, but you need to develop a good strategy to take full advantage of it, according to a paper authored by Cadence and Broadcom and presented at the recent DVCon conference . The paper detailed Broadcom's experience using transaction...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 23 2011
Achieve the Next Level of Verification Productivity with Specman Advanced Option
Advanced verification customers are seeing their verification environments getting more and more complex requiring millions of lines of code spread across hundreds, even thousands of files that are re-used from Block --> SoC --> System level. Today's design under test (DUT) can be extremely...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Jan 18 2011
How I Nearly Had My Own “Subtract Bug” in a CPU Design
In a recent blog post , I talked about learning a public lesson on the importance of software verification while an intern at Digital Equipment Corporation (DEC). Since I spent most of my early career as a logic designer, not a programmer, I figure that an example of a corner-case condition from that...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Tue, Jan 4 2011
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