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Functional Verification,Specman

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-) A customer reported a random stability issue, explaining that the generator (IntelliGen) generated different values with the same...

Posted to Functional Verification (Weblog) by teamspecman on Mon, Jan 21 2013
Avoid Overly Long Expressions in Specman e Code

When you write your e code, a good practice is to avoid expressions that are "overly long" even though they are completely legal. While there is no hard definition of what constitutes an overly long expression, such long expressions can lead to human errors and parser processing errors. Very...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Dec 11 2012
UVM e vr_ad -- Specman Read/Write Register Enhancements

If you are a Specman vr_ad user, you probably know that register access is implemented using the read_reg / write_reg. For reading/writing a register, you have to 1. Extend a vr_ad_sequence 2. Add a field of the type of the register you want to access 3. In the body() , call the read/write_reg For example...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Nov 23 2012
Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are Available Now

Recently an EDA industry observer relayed some Specmaniacs' concerns about satisfying the increasing demand for e/Specman trained verification engineers in Europe and other geographies. Team Specman is seeing this growth too, and here is what we [Cadence] are doing to help: * First, we have a network...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Nov 16 2012
Function Level C Interface – New C Interface for Specman

Working with the conventional Specman C language interface has two major disadvantages: 1. There is a tight dependency between the e code and the C code. The user must include the Specman header file which was generated based on the e code. Every minor change in the e code requires regeneration of the...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Nov 6 2012
Re: time between two events

you have sys.time and sys.realtime. You can log the time value when an event happens (using for example and on block) and next time you can calculate the delta. -hannes

Posted to Functional Verification (Forum) by hannes on Thu, Oct 11 2012
Using pli_access for Stubless Indexed Ports

Indexed ports are used to access composite HDL objects in SystemVerilog (SV). Their most frequent use is to access SV multi-dimensional arrays by defining a simple indexed port and accessing the array elements with the port indexes. Ports in general, and Indexed ports specifically, are static objects...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Oct 9 2012
Webinar: New Interface Links Specman e Language to SystemC TLM Models

As the use of SystemC transaction-level models (TLM) increases in verification environments, there's a growing need to connect SystemC TLM 2.0 models to hardware verification language testbenches. A newly archived webinar details a new interface that links the Specman e language to SystemC TLM 2...

Posted to Industry Insights (Weblog) by rgoering on Mon, Sep 17 2012
UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation. Specman has a very robust implementation of reset during test, which imitates a return to cycle 0. All threads are terminated, the run() method is called again, and evaluation of temporal expressions is restarted. UVM...

Posted to Functional Verification (Weblog) by teamspecman on Wed, Sep 5 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models

SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 13 2012

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Functional Verification,Specman

Specman: An Assumed Generation Issue and its Real Root Cause

Avoid Overly Long Expressions in Specman e Code

UVM e vr_ad -- Specman Read/Write Register Enhancements

Need e/Specman Expertise ASAP? Free Training and Verification Alliance Partners Are Available Now

Function Level C Interface – New C Interface for Specman

Re: time between two events

Using pli_access for Stubless Indexed Ports

Webinar: New Interface Links Specman e Language to SystemC TLM Models

UVM Testflow Phases, Reset and Sequences

Whitepaper: Connecting Specman e Language to SystemC TLM Models