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Functional Verification,Industry Insights,Incisive,verification
Accellera
Adam Sherer
Advanced Profiler
assertion-based verification
C language
C/C++
Cadence
cause analysis
CDNLive!
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Chinmay Banerjee
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Debug
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Functional Verification Survey -- Why Gate-Level Simulation is Increasing
In a recent webinar on increasing functional verification performance, the point was made that gate-level simulation usage is increasing. Wait a minute, I thought - haven't we spent the last two decades talking about raising the abstraction level for design and verification? While some IC verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jan 16 2013
Software-Driven Verification – a Hot Topic for 2013?
Many engineers today use C language software running on an embedded processor model to build testbenches for hardware verification. This "software-driven verification" technique is an ad-hoc methodology that often uses home-grown tools. But it's something you may hear more about in 2013...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Jan 3 2013
Archived Webinar: New Technology Attacks the Verification Debug Bottleneck
Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 29 2012
Whitepaper: Connecting Specman e Language to SystemC TLM Models
SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 13 2012
Webinar: Speeding UVM SystemVerilog Simulation With Software Engineering Techniques
You may be a software engineer and not even know it. If you develop IC verification environments, the way you write and optimize code has a tremendous impact on simulation performance. A recently archived Cadence webinar provided a number of practical tips to help you analyze and optimize Universal Verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Aug 8 2012
Whitepaper: Verification Performance is More Than Raw Simulation Speed
RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster,...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jan 31 2012
Archived Webinar: Bringing SystemC and C/C++ Models into UVM
If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 7 2011
CDNLive! - How To Succeed At Formal Verification
Four customer presentations at CDNLive! Silicon Valley , held Oct. 5-16, provided some valuable tips for users and prospective users of formal verification tools. The presenters included three users of Cadence Incisive Formal Verifier (IFV) and one user of the recently announced Incisive Enterprise Verifier...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Oct 15 2009
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