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Functional Verification,Industry Insights,Incisive,TLM

  • Whitepaper: Connecting Specman e Language to SystemC TLM Models

    SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 13 2012
  • Archived Webinar: Bringing SystemC and C/C++ Models into UVM

    If you use or plan to use C language models for verification - be they SystemC, C, or C++ -- you will probably want to connect them to a SystemVerilog verification environment. How can this be done? A newly archived Cadence webinar has the answer - use the multi-language support capability that Cadence...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 7 2011
  • At DVCon 2011 Next Week

    Next week my colleagues and I will be at DVCon 2011 in force, ready to regale you with technical papers, panels, and techtorials covering the full range of functional, assertion-based, mixed-signal, and transaction-level verification topics. If you are within a tank of gas or a Southwest flight of San...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Feb 25 2011
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