Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Functional Verification/Incisive/e language
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Functional Verification,Incisive,e language
AF
AOP
Aspect Oriented Programming
assumed generation
Axel Scherer
Cadence
Constrained random
coverage
cowbell
CS348
debug
define-as
Duracell
e code
EDA
eRM
Ernie
Funcional Verification
garbage
garbage collection
generation
generic payload
hardware verification
hvl
IEEE 1647
IES
IES-XL
Incisive Enterprise Simulator
Incisive Enterprise Simulator (IES)
Industry Insights
Infinity minus
IntelliGen
interface additions
license search
licenses
lists
macros
managing memory
memory
memory errors
memory management
metric driven verification (MDV)
MOOC
new features
on-line class
on-line course
random generation
Scherer
simulation
SimVision
SoC
Specman
Specman data
specman elite
Specman garbage collection
Specman licenses
Specman/e
Stimulus
stop simulation
stop Specman
SystemC
SystemVerilog
team specman
test generation
testbench
Testbench simulation
TLM
TLM 2.0
transaction-level modeling
Udacity
universal verification methodology
URM
UVC
uvm
UVM training
UVM tutorial
uvmworld.org
verification
verification course
Verification methodology
verification tutorial
video
video tutorial
vManager
vPlan
whitepaper
writing macros
YouTube
Zander
Mode Support for SimVision “Stop Simulation” Button
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in the simulation. To provide better flexibility in the exact place where you want to pause, the...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Wed, May 8 2013
Launch Time – Udacity CS348 Functional Hardware Verification Hits the Web Today, March 12, 2013
Coinciding with the first day of CDNLive! Silicon Valley, our Udacity MOOCs course on Functional Hardware Verification will go live today! Developing this course has been a very rewarding experience and we are happy this day has finally come. Last week we gave you a sneak preview of the interactivity...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Tue, Mar 12 2013
Specman: An Assumed Generation Issue and its Real Root Cause
Random generation is always a complex task, and differences in results are usually very hard to debug. Besides, generation misbehavior always rings many bells in R&D :-) A customer reported a random stability issue, explaining that the generator (IntelliGen) generated different values with the same...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Jan 21 2013
Whitepaper: Connecting Specman e Language to SystemC TLM Models
SystemC Transaction-Level Modeling (TLM 2.0) is coming into widespread use for virtual platforms and high-level verification, but the benefits of TLM models will be limited if there's no connection to more conventional hardware verification languages. A recently published whitepaper in the Cadence...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 13 2012
Constrained Random Test Generation In e [IEEE 1647], Ernie * Duracell ≈ Infinity Minus
Ernie & Duracell "I feel great" - long pause - "I feel great, I feel great". 6 weeks later: "I feel great, I feel great, I feel great" - pause - "I feel great". I hear this sound coming out of my son's room. What is going on in my house? Is there such a...
Posted to
Functional Verification
(Weblog)
by
Axel Scherer
on Wed, Aug 1 2012
Using Flexible Specman License Searches
Until recently, Specman used to look for its licenses in the following strict, hardcoded order: Either 1. "Incisive Specman Elite" 2. "Incisive Enterprise Simulator" 3. "Incisive Enterprise Verifier" Or 1. "Incisive Enterprise Simulator" 2. "Incisive Enterprise...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Mon, Jul 9 2012
Tips on Writing Macros in Specman e Language
In this blog, I will present some tips that can be very useful when you write e macros. We will see which kind of macro we should use for our purposes, and what options we can use to better define our macro. Let's begin by looking at the following simple example. Assume that you want to define a...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, May 22 2012
Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage”)
Memory management is not something the Specman user is supposed to worry about. Nobody likes to make notes about allocations and freeing up memory segments when he's programming, and Specman supplies a mechanism that allows the programmer to have some extra time for a cup of coffee. Unfortunately...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Fri, May 11 2012
Specman Application Note: Improving Verification Productivity With Dynamic Load and Reseeding
Are you looking for new approaches to improve your verification productivity by 40 - 60%? Look no further... read the technical application note by Corey Goss on how to Improve Verification Productivity through Adopting Dynamic Load and Reseed Methodology. Attached is a link to the application note that...
Posted to
Functional Verification
(Weblog)
by
teamspecman
on Tue, Mar 1 2011
Page 1 of 1 (9 items)