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Functional Verification

  • Comment Direct From XJTAG, Ltd.

    Simon Payne, the CEO of XJTAG, has responded to my invitation to comment on their trade show strategy -- his message is reproduced in full below. Please post your comments here for the benefit of whole the community, or contact XJTAG apart from this forum via http://www.xjtag.com/company/contact.php...
    Posted to Functional Verification (Weblog) by jvh3 on Mon, Aug 24 2009
  • Specman 9.2 Preview: Named Constraints

    [Preface: all features in the 9.2 preview series are in Beta now. We invite you to sign-up for the beta program and give this feature a test drive!] [Team Specman welcomes Reuven Naveh from Specman R&D to introduce “his” new feature.] Abstract In Specman 9.2 we are extending the syntax...
    Posted to Functional Verification (Weblog) by teamspecman on Fri, Aug 21 2009
  • Survey Results and Commentary on The XJTAG Girls at DAC 2009

    In my last post, I recounted the disproportionate buzz received by the "XJTAG Girls" , a pair of sales models stationed in the booth of XJTAG, Ltd. , a supplier of IEEE 1149.1 boundary scan development tools. The surprisingly strong reactions to this classic trade show strategy prompted me...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Aug 19 2009
  • A Quick Look Back at DAC

    Well, I had good intentions of blogging from DAC , or at least summarizing my four days there when I was back in the office on Friday (July 31). But I returned to a very busy week of actiivties that got bunched up together partly because so many Cadence people were at the show. At this point, I can offer...
    Posted to Functional Verification (Weblog) by tomacadence on Mon, Aug 10 2009
  • Post-DAC 2009 Survey on The XJTAG Girls

    One non-technology item that received an extraordinary buzz at DAC 2009 were the XJTAG Girls: For those of you not at DAC, these sales models were effective in persuading passers by to trade contact info for a chance to win a portable GPS or iPod. Of the 5,135 combined exhibits-only and conference attendees...
    Posted to Functional Verification (Weblog) by jvh3 on Fri, Jul 31 2009
  • DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

    Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able to make public what we have in store for you in Specman/IES-XL version 9.2 this September. Additionally, consider this post an open invitation to join the 9.2 beta program that officially starts next week on Monday August...
    Posted to Functional Verification (Weblog) by teamspecman on Mon, Jul 27 2009
  • FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

    The mighty FSM – you first learned it when you were a young pup at University (some of you still are!) and you use it day in and day out today. Such a simple concept – I’m in a known state and I will either remain here or move to a new state based on inputs – but a difficult one...
    Posted to Functional Verification (Weblog) by Team genIES on Thu, Jul 23 2009
  • DAC '09 for the Specmaniac

    The following are the "must see" items for Specmaniacs lucky enough to get travel authorization for DAC 2009 (and/or who scored a cheap ticket on Priceline.com for a spur of the moment "vacation" to scenic San Francisco). 1 - Specman in the Cadence Main Booth (#3751, North Hall) Given...
    Posted to Functional Verification (Weblog) by teamspecman on Wed, Jul 22 2009
  • At DAC Next Week

    Yours truly will be at the big show next week, and I hope that all of you in the blogosphere will be able to sweet talk your management into letting you go as well. For those of you who have already won a golden ticket: * By all means let's meet in person. When not in a customer or partner meeting...
    Posted to Functional Verification (Weblog) by jvh3 on Wed, Jul 22 2009
  • Simulation of Voltage Scaling for Dynamic Power Reduction

    Some background info: In a previous blog , I introduced: DVFS (Dynamic Voltage and Frequency Scaling), a technique used for Dynamic Power Reduction. RVM (Real Valued Modeling) for efficient simulation of mixed signal SoC with very high speed and efficiency using Cadence DMS (Digital Mixed Signal) offerings...
    Posted to Functional Verification (Weblog) by Neyaz on Wed, Jul 22 2009
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