Log In
|
Register
|
Resource Library
|
Worldwide
Asia-Pacific
|
China
|
EMEA
|
India
|
Israel
|
Japan
|
Korea
|
Taiwan
|
Global Office Locator
Solutions
Products
Services
Support & Training
Alliances
Community
About Cadence
Solutions:
Design IP
Mixed-Signal
Low-Power
Advanced Node
3D-IC
Enterprise Verification
Hosted Design
System Development Suite
Solutions Home
Products for:
System Design and Verification
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
More Products
OrCAD Products
Sigrity Technologies
Design IP
Verification IP
IP Catalog
Products A-Z
Products Home
Capabilities and Practices
Methodology Services
Design Services
DFM Services
Educational Services
Programs
SOI Design Hub
Services Home
Support
Support Offerings
Support Process
Cadence Online Support
Software Downloads
Computing Platform Support
University Software Program
Training
Training Options
Training Course Catalogs
Support & Training Home
Programs and Initiatives
System Realization Alliance
Foundry Program
ChipEstimate.com - Chip Planning Portal
Connections Program
Verification Alliance Program
Channel Partner (VARs) Program
Power Forward Initiative
Standards and Languages
PCB Service Bureaus
Industry Memberships
Alliances Home
Communities
Industry Insights Blog
Low Power Blog
Mixed-Signal Design Blog
System Design and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
Quicklinks
All Blogs
All Forums
Community Search
CDNLive User Conferences
Community Home
EDA Vision
Visit the EDA360 microsite
News and Events:
Newsroom
Events and Webinars
Resources:
Customer Success
Newsletters
Publications
Multimedia Center
Logos
Company Info:
Investor Relations
Executive Team
Careers
Contact Us
About Cadence Home
Home
>
Community
>
Tags
> Freescale
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.
Register
|
Membership benefits
Get email delivery of the Cadence blog (individual posts).
Industry Insights
Low Power
Mixed-Signal Design
System Design
and Verification
Cadence IP Blog
Functional Verification
Logic Design
Digital Implementation
Custom IC Design
RF Design
PCB Design
IC Packaging and SiP Design
Silicon Signoff and Verification
All Blog Categories
Popular Tags
Allegro
Analog
ARM
cadence
DAC
Digital Implementation
e
EDA360
encounter
ESL
functional verification
Incisive
industry insights
Low power
Mixed-Signal
OVM
PCB
PCB design
Specman
System Design and Verification
SystemC
TLM
UVM
Verification
Virtuoso
Browse All Tags
Email
*
Required Fields
Recipients email
*
(separate multiple addresses with commas)
Your name
*
Your email
*
Message
*
Send yourself a copy
Share
Twitter
Facebook
LinkedIn
Google+
Subscribe
RSS
Cadence RSS Feeds
Cadence Press Releases
System Design and Verification Blog
Functional Verification Blog
Digital Implementation Blog
Custom IC Design Blog
RF Design Blog
PCB Design Blog
IC Packaging and SiP Design Blog
Manufacturability Signoff Blog
All Blogs
System Design and Verification Forum
Functional Verification Forum
Digital Implementation Forum
Custom IC Design Forum
Custom IC SKILL Forum
Logic Design Forum
RF Design Forum
PCB Design Forum
PCB SKILL Forum
IC Packaging and SiP Design Forum
Manufacturability Signoff Forum
Intro copy of the newsletter section here, some intro copy of the newsletter. Instruction of how to subscribe to this newsletter.
Contact Us
Cadence Contacts
Community Relations
Customer Support
Employment
Investor Relations
Media Relations
Training
Global Office Locator
Find Offices worldwide
»
Sales Inquiry
Request for Product information
»
Cadence Channel Partners
»
Corporate Headquarters
Cadence Design Systems, Inc.
2655 Seely Avenue
San Jose, CA 95134
Phone: 408.943.1234
*
Required Fields
First Name
*
Last Name
*
Email
*
Company / Institution
*
Comments:
*
Send Yourself A Copy
Freescale
Accelerated Verification IP
accelerated VIP
acceleration
AMD
Anis Jarrar
ARM
back bias
Berkeley Wireless Research Center
body bias
broadcom
BWRC
C to Silicon
C++
Cadence
Calypto
Cambridge
case splitting
case-splitting
CDN Live
CDNLive
CDNLive!
charge pump
Chris Komar
Clem Meas
CMP
Custom IC Design
DAC
DAC 2012
DAC breakfast
DAC panel
design for manufacturability
DFM
DFY
Doulog
DVCon
DVFS
Dynamic power
dynamic power analysis
ECO
EDA360
embedded
embedded software
Emulation
Encounter
Ericsson
ESL
ESL Market
flip-flops
Formal
Formal Analysis
formal verification
Formal Verifier
foundries
FPGA
FPGA Based Prototyping
FPGA prototyping
FPGA-based prototyping
Frank Schirrmeister
Functional Verification
GlobalFoundries
ground level shifter
High-level Synthesis
hls
in-circuit acceleration
Incisive
Industry Insights
Jan Rabaey
Kinetis
low power
Low Power Mixed Signal Verification
Low Power Summit
low-power
low-power design
LSI
mixed signal
mixed-signal
MSV
multi-bit flops
MVt
Palladium
Palladium XP
physical IP
POP
power analysis
power gating
power management
power optimization
power shut-off
Samsung
ST Microelectronics
System Development Suite
SystemC
system-level design
TLM
verification
Verification Computing Platform
Verification IP
VIP
virtual platforms
Xilinx
CDNLive! -- The Other Side of the Low Power Design Techniques
In a recent CDNLive! Silicon Valley presentation titled "Low Power Implementation on the Freescale Kinetis Family," Annis Jarrar from Freescale demonstrated how various low power design techniques were used in the popular Kinetis low power platform. These techniques included power gating with...
Posted to
Low Power
(Weblog)
by
QiWang
on Thu, Mar 29 2012
Customer, Partner DFM Concerns Spur New Methodologies
Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 7 2012
Webinar Report: New Methodology Revs Up Code Coverage Analysis
Most IC verification teams use code coverage as signoff criteria, but they often have limited information about unreachable code. A new "case-splitting" methodology, described in a recently archived webinar, shows how a technique based on formal analysis provides new insight into coverage holes...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Feb 6 2012
High Level Synthesis for a Control-Dominated Design?
CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Thu, Dec 15 2011
Freescale DAC Keynote: EDA Support Needed for Multi-Core Embedded Devices
Lisa Su, senior vice president and general manager at Freescale Semiconductors, needs some help from the EDA community. In a dynamic keynote speech at the Design Automation Conference June 7, she set forth a list of hardware and software design tool requirements for the oncoming generation of multi-core...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Jun 8 2011
User Experience: Optimizing Power and Area With Formal Verification
Formal verification can be a powerful tool for low-power design optimization, according to a paper authored by Cadence and Freescale and presented at the recent DVCon conference. The paper showed how formal property checking can validate whether retention flip-flops are controllable, and identify those...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 17 2011
Video: Optimizing Area and Power Using Formal Methods
At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV). Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Mar 8 2011
Users Outline New Approaches To Mixed-Signal Verification
At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 2 2009
Freescale Technologist Eyes Move To SystemC And TLM
Are SystemC and TLM-driven design ready to replace RTL? That’s the title of a Design Automation Conference lunch panel moderated by Mark Johnstone, chief technologist for Freescale Semiconductor’ s Flow and Methodology Development Organization. Realizing that Johnstone probably has a unique...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Jul 21 2009
Latest Virtuoso news from CDNLive!
Hey Folks, thanks to all of you who participated in CDNLive SV. There was a lot of great information shared by our customers as to their success using teh latest Virtuoso (which by the way has a new version IC6.1.3 out on downloads). Three presentations that I would call your attention to come from our...
Posted to
Custom IC Design
(Weblog)
by
NewYorkSteve
on Mon, Sep 22 2008
Page 2 of 2 (20 items)
< Previous
1
2