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User Experience: Optimizing Power and Area With Formal Verification
Formal verification can be a powerful tool for low-power design optimization, according to a paper authored by Cadence and Freescale and presented at the recent DVCon conference. The paper showed how formal property checking can validate whether retention flip-flops are controllable, and identify those...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Mar 17 2011
A Modest Proposal: Using Formal to Close Coverage Gaps
In my last blog post , I summarized some of our activities at DVCon and mentioned briefly the "Birds of a Feather" (BoF) panel and discussion on "Strategies in Verification for Random Test Generation: New Techniques and Technologies" held Monday evening. Today I'd like to fill...
Posted to
Functional Verification
(Weblog)
by
tomacadence
on Fri, Mar 11 2011
Video: Optimizing Area and Power Using Formal Methods
At DVCon 2011, a paper presented by Freescale and Cadence described a truly novel application of formal technology for something completely different than assertion-based verification (ABV). Specifically, the authors used formal engines to optimize the selection of complex (read, "higher in area...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Mar 8 2011
Formal Driven MDV – A New Tool for your Toolbox
Have you considered adding formal to your metric driven verification flow? Maybe now is the time, as it has never been easier within Incisive Enterprise Manager to combine results coming from formal assertions with results coming from simulation, and visualize both at the same time. You see the results...
Posted to
Functional Verification
(Weblog)
by
Team MDV
on Mon, Feb 21 2011
The Role of Coverage in Formal Verification, Part 3
.special { font-family: 'Courier New' !important; } In the last post of this series, we will address the last but not least of three key questions to be answered with coverage in formal verification: How good are my formal constraints? (Addressed in Part 1 ) How good is my verification proof...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Mon, Feb 14 2011
The Role of Coverage in Formal Verification, Part 2 Continued…
Recall that three main questions need to be answered to attain coverage in formal verification: Part 1 of this series addressed, "How good are my formal constraints?" In Part 2 we showed debugging of over-constraining with help of examples, addressing the question, "How good is my verification...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Jan 27 2011
Video: Distinguished Engineer Alok Jain on Formal and Assertion-Based Verification (ABV), Today and Tomorrow
Kicking off 2011, my colleague Alok Jain -- a Distinguished Engineer at Cadence who directs the company's R&D efforts in formal verification -- spoke with Industry Insights columnist Richard Goering . In a wide ranging interview they discussed formal verification usage trends, benefits, roadblocks...
Posted to
Functional Verification
(Weblog)
by
jvh3
on Sun, Jan 23 2011
The Role of Coverage in Formal Verification, Part 2
As noted in the prior installment of this series, there are three main questions to be answered with coverage in formal verification: How good are my formal constraints? How good is my verification proof? How can I feel confident my verification is complete? In Part 1 we began to address the first question...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Thu, Jan 20 2011
More on the Benefits of Metric-Driven Formal Analysis and Verification (MDV + ABV + IEV)
We interrupt R&D's Vinaya Singh's excellent series on "The Role of Coverage in Formal Verification" to reference a related post from Richard Goering on "Extending Metric-Driven Verification (MDV) to Formal Analysis - What, Why, and How" . Specifically, Richard's article...
Posted to
Functional Verification
(Weblog)
by
TeamVerify
on Tue, Jan 11 2011
Extending Metric-Driven Verification to Formal Analysis – What, Why, and How
In a Jan. 10 announcement of new Silicon Realization verification capabilities, Cadence has promised to "extend metric-driven verification from digital simulation to formal model checking." Here's some more detailed information about what that means and how it can help design and verification...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jan 10 2011
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