Cadence.com will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST).
Cadence.com login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Tags > Floorplanning
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Floorplanning

  • SOC Encounter :: Layout Routing Issues

    Hi I am facing a problem with the layout generated by Encounter. I am unable to route the design properly. After setting up the Floorplan of the design when I place the Standard Cells, it also routes the metals and the metals are overlapped. Also it doesn't use the standard rules like using M1 Horizontal...
    Posted to Digital Implementation (Forum) by Sohaib Qazi on Wed, Feb 8 2012
  • Re: SOC Encounter :: LEF File load Failed

    Hi, I found the problem and resolved. Actually I was not using any Floorplanning while taking the pic that I shown before. Now I am facing another problem. I am unable to route the design properly. After setting up the Floorplan the design when I place the Standard Cells it also routes the metals as...
    Posted to Digital Implementation (Forum) by Sohaib Qazi on Wed, Feb 8 2012
  • Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

    A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
  • Re: pin placement around core in encounter

    Hi, You can use editPin command in way to place IO pins on boundary of the block. Just example from documentation (Encounter Digital Implementation System Text Command Reference): Example: The following command modifies the pins as specified here: - the command runs on the module DTMF_CORE_INST1 - the...
    Posted to Digital Implementation (Forum) by mikhail on Tue, Nov 22 2011
  • EDA “Nobel Prize” Goes to Algorithmic Pioneer

    The annual Phil Kaufman award, which honors individuals who have made a significant impact on electronic design automation, is the EDA industry's equivalent of the Nobel Prize. This year's award was presented Nov. 8 at a dinner event in San Jose, California, sponsored by the EDA Consortium and...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 10 2011
  • How do I control where the routing tracks start?

    I am creating a floorplan in Encounter 9.14-s274_1. I have an updated technology lef and I am regenerating my abutted floorplan. The problem is that I have to maintain the pin locations of the subblocks. The new lef has changed the routing directions of each layer, so M1 went from horizontal to vertical...
    Posted to Digital Implementation (Forum) by PSmoot on Fri, Nov 4 2011
  • Managing ECOs in Mixed Signal Designs

    Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation...
    Posted to Mixed-Signal Design (Weblog) by Benatcdn on Thu, Sep 29 2011
  • Proving that a given netlist A results in better layout than netlist B

    Hi, I have a very general question, I have two netlists A & B, basically same functionality but somewhat different synthesis( though mapping to same library) in front end. I need to see which one of them is doing better in terms of layout. What parameters can I use to compare two layouts from soc...
    Posted to Digital Implementation (Forum) by asinghct on Wed, Jun 29 2011
  • Multiple Pin Metal Layer

    Hi friend I need an urgent help in the inplementations of a hierarchical block. In my design i need to use multiple metal layer for a some input/output pins.Presently i am using MET4 for the pins. I need the same pins in MET2,MET3 and MET4. Please suggest the way to impement this in EDIS
    Posted to Digital Implementation (Forum) by Kevin P Thomas on Thu, Jun 16 2011
  • Mixed-Signal Physical Design Implementation Made Easy

    Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution...
    Posted to Mixed-Signal Design (Weblog) by RajendraPratap on Thu, Jun 16 2011
Page 2 of 4 (36 items) < Previous 1 2 3 4 Next >