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FPGA

Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More

If you want a deeper understanding of the challenges, trends, and potential new solutions for IC and systems design, there's no better place to find out than the IEEE-sponsored Electronic Design Processes Symposium (EDP) April 5-6, 2012, in Monterey, California. Now in its 19 th year, this interactive...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 8 2012
DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Will systems-on-chip (SoCs) become so expensive to design that people are going to buy chips off the shelf, and differentiate products through software alone? That's one question that was put before a panel of EDA industry experts at the DVCon conference Feb. 29, 2012. Short answer -- no, but we...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 1 2012
Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB SI

Altera and Cadence recently collaborated and completed correlation work with Allegro PCB SI using IBIS-AMI models for the Altera Stratix® V FPGAs. Customers may now contact Altera and request IBIS-AMI models for the Stratix V that support all data rates from 6 0 0 Mbps to 28 G b ps. The state of...

Posted to PCB Design (Weblog) by TeamAllegro on Fri, Feb 24 2012
Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17 th North American SystemC User Group meeting ( NASCUG ), will take place this coming Monday (Feb. 27, 2012) at the DoubleTree Hotel in San Jose, CA. I am on the agenda with a presentation called "Extending Fixed Sub-systems at the TLM Level - Experiences from the FPGA World", in which...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Feb 23 2012
High Level Synthesis for a Control-Dominated Design?

CDNLive! conferences are full of interesting and helpful presentations by customers as well as Cadence engineers. However, it's easy to miss good presentations due to the fact that tracks run in parallel, and also due to the fact that these conferences occur regionally. The good news is that if you...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, Dec 15 2011
Welcome to the Zynq-7000 Virtual Platform

As you might guess we are pretty excited about the Virtual Platform development for the Zynq-7000 EPP . The FPGA world has changed a lot from 1995 when I was an FAE at Cypress Semiconductor selling and supporting programmable logic devices. This was during the transition from schematic capture to HDLs...

Posted to System Design and Verification (Weblog) by jasona on Fri, Oct 28 2011
Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

You would expect a unique semiconductor product to have a unique software development environment. That is the case with the Xilinx Zynq-7000 family, an Extensible Processing Platform (EPP) that includes a dual-core ARM Cortex-A9 processor and a 28nm FPGA fabric. Today (Oct. 26, 2011) at ARM TechCon...

Posted to Industry Insights (Weblog) by rgoering on Wed, Oct 26 2011
What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!

The 16.5 release of the Allegro System Connectivity Manager (SCM), also known as Allegro System Architect (ASA), has been enhanced to view implicit power pins in the Component Connectivity Pane (CCP). This is required for control over the power pins for the design with dies or FPGAs where an ECO is required...

Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Aug 30 2011
Video: IP Ecosystem Helps Xilinx Become a “Platform Provider”

Xilinx is making a shift from being a silicon provider to a platform provider, according to David Tokic, director of partner ecosystem alliances at Xilinx. As such, the company is increasingly relying on a broad ecosystem that includes silicon IP, EDA, and services. In a video interview at the recent...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 20 2011
Q&A: A Closer Look at the Cadence Rapid Prototyping Platform

Cadence entered a new marketplace with the recent introduction of the Rapid Prototyping Platform , an FPGA-based prototyping environment that supports pre-silicon software development and system validation. The Rapid Prototyping Platform is part of the tightly integrated System Development Suite , which...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 1 2011

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FPGA

Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB SI

Virtual Divide and Conquer Enables Fixed Sub-Systems

High Level Synthesis for a Control-Dominated Design?

Welcome to the Zynq-7000 Virtual Platform

Virtual Platform for Xilinx Zynq – Why “Extensible” Matters

What's Good About Power Pins in SCM? The Secret's in the 16.5 Release!

Video: IP Ecosystem Helps Xilinx Become a “Platform Provider”

Q&A: A Closer Look at the Cadence Rapid Prototyping Platform