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FPGA

What's Good About FSP’s Design Compare? Check Out 16.6!

The 16.6 Allegro FPGA System Planne r (FSP) product has an extremely helpful Design Compare capability. With design changes done in Allegro PCB Editor the FSP designer needs to verify and, if they agree, accept the PCB designer’s changes. The FSP Design Compare form compares two FSP designs and...

Posted to PCB Design (Weblog) by Jerry GenPart on Thu, Apr 18 2013
DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

If you want to organize an interesting panel discussion, think big - really big. J.L. Gray, vice president of Verilab and author of the Cool Verification blog , did just that with a DVCon 2013 panel, where he asked panelists what will be required to reach 1 million new semiconductor design starts per...

Posted to Industry Insights (Weblog) by rgoering on Fri, Mar 1 2013
What's Good About FSP Planning Mode? Check Out 16.6!

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto-interactive pin swap (“Planning Mode”) with the addition of “Auto pinswap” functionality. Using three different algorithms – Reassign Bundle Pins, Rake Order, and Breakout Order –...

Posted to PCB Design (Weblog) by Jerry GenPart on Tue, Jan 29 2013
Mixed-Signal simulations on FPGA using batch file

Hi, I am trying to design an ADC simulation on Cadence but my professor says that I can simulate the analog portion on Cadence and then output the simulation values in a batch file. Using the values in the batch file as inputs to the FPGA (Xilinx Virtex-6), which has the rest of the digital circuit of...

Posted to Mixed-Signal Design (Forum) by aliasnikhil on Tue, Jan 8 2013
Changing the Game with Processor Based Emulation

I have always been fascinated by game changing moves. Some are more successful than others, but the general principle is always the same - coming with a gun to a knife fight. Two of my favorites are from sports. When I was a young rower, the moving outrigger was a game changer for a while and was a fascinating...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Oct 11 2012
C-to-Silicon Japan User Group and Ikegami Production Experience

We have been seeing some rapid growth in adoption of C-to-Silicon Compiler high-level synthesis. Given that it is a new way of doing design, we have been holding user local groups to get customers together with Cadence people to share experiences, information, and ideas so that we can all benefit. We...

Posted to System Design and Verification (Weblog) by Jack Erickson on Tue, Jul 3 2012
DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

John Blyler, Editorial Director at Extension Media , presented in our EDA360 Theatre at DAC 2012 about "ASIC/ASSP Prototyping with FGPAs" and provided an update on his annual survey on this topic. The current 2012 survey is actually currently ongoing and you can still participate here . FPGA...

Posted to System Design and Verification (Weblog) by fschirrmeister on Thu, Jun 28 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First

SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jun 25 2012
DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises...

Posted to Industry Insights (Weblog) by rgoering on Thu, Jun 14 2012
Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More

If you want a deeper understanding of the challenges, trends, and potential new solutions for IC and systems design, there's no better place to find out than the IEEE-sponsored Electronic Design Processes Symposium (EDP) April 5-6, 2012, in Monterey, California. Now in its 19 th year, this interactive...

Posted to Industry Insights (Weblog) by rgoering on Thu, Mar 8 2012

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FPGA

What's Good About FSP’s Design Compare? Check Out 16.6!

DVCon 2013 Panel: 1 Million IC Design Starts – How Can We Get There?

What's Good About FSP Planning Mode? Check Out 16.6!

Mixed-Signal simulations on FPGA using batch file

Changing the Game with Processor Based Emulation

C-to-Silicon Japan User Group and Ikegami Production Experience

DAC 2012: The Top Seven Reasons for using FPGA Based Prototyping

High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First

DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

Join EDA “Movers and Shakers” at IEEE EDP Symposium – Cloud, 3D-ICs, Power and More