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FED
apropos
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ple physical global
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TeamFED
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yield
Logic Design and Test Design: Do they need each other?
Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important...
Posted to
Logic Design
(Weblog)
by
Ed JM
on Sat, Apr 17 2010
Cadence and Very Cool Stuff
One of the very cool things about my job is that I get to see all kinds of new stuff early. I’m privileged to be involved in technology roll outs, and so get to be involved in early discussions with R&D, Product Engineering, and Marketing. And, I gotta tell you, there is very cool stuff coming...
Posted to
Digital Implementation
(Weblog)
by
Rich Owen
on Tue, Nov 3 2009
DesignWare and AmbitWare Demystified - Why and When to Avoid?
By Diego Hammerschlag Sr. Technical Leader Team FED Most, if not all, synthesis tools today support the use of Synopsys DesignWare or a vendor specific brand of <vendor>Ware such as Ambit's AmbitWare, Cadence's ChipWare and others. I have been frequently asked on the purpose of <vendor>Ware...
Posted to
Logic Design
(Weblog)
by
Team FED
on Fri, Jul 24 2009
Of Rights & Wrongs: The Bottom-up vs. Top-down Methododology Debate
By Diego Hammerschlag Sr. Technical Leader Team FED The top-down vs. bottom-up methodology decision is one that design engineers should not take lightly. It carries ramifications throughout the hole flow and can certainly make or break a project if not careful. Such methodology decision can impact: Quality...
Posted to
Logic Design
(Weblog)
by
Team FED
on Mon, Jun 22 2009
Why Your Project Should Not Follow the Fate of the Mars Orbiter - Part I
By Diego Hammerschlag Sr. Technical Leader Team FED The “Orbiter” was a spacecraft on a mission to study the planet Mars. Unfortunately, Lockheed Martin and NASA had a mix up using Imperial units (pounds, miles, etc.) and Metric units (kilometers, kilograms, etc.) Bad things happen to spacecraft...
Posted to
Logic Design
(Weblog)
by
Team FED
on Mon, May 25 2009
Don't Let Power Kill Your Project - What % LVT Should I Use?
By Diego Hammerschlag Sr. Technical Leader Team FED A common question or requirement that designers have is the percentage of low voltage threshold (LVT) cells that should be allowed in a design. For those not familiar with LVT cells, they are special cells that have a lower voltage threshold and can...
Posted to
Logic Design
(Weblog)
by
Team FED
on Wed, May 13 2009
Ah, Power! Now Can I Drive?
Last week a large number of customers and potential customers attended the “System-level Design & Chip Architecture for Low-Power ICs Techtorial and Workshop” sessions in Irvine, San Diego, and San Jose. They must have been monitoring sub-space communication channels or read this blog...
Posted to
Logic Design
(Weblog)
by
Mike Carrell
on Fri, Apr 24 2009
New InCyte v3.5 Let’s You Manage Power, Without Being the “Power Expert”
Quantify the trade-offs of Power Management techniques in Early Chip Planning with the new v3.5 release of Chip Planning Solutions . The Chip Planning Solutions team, who comes to Cadence via acquisition of ChipEstimate.com about one year ago, has just released a new version of InCyte . You may be familiar...
Posted to
Logic Design
(Weblog)
by
Mike Carrell
on Fri, Apr 3 2009
Where Oh Where is "number_of_routing_layers"?
OK, I'll just do " set_attribute number_of_routing_layers 6 "... Error : The attribute is read-only. [TUI-26] [set_attribute] : attribute: 'number_of_routing_layers', object type: 'root' : Cannot set or reset read-only attributes. Hey, wait a minute! If you are faced with...
Posted to
Logic Design
(Weblog)
by
mrardon
on Wed, Mar 18 2009
Introducing "Team FED"
Today we are launching the "Team FED" blog. Similar to some of the other "Team" blogs here at Cadence, this will be focused on technical tips and tricks to help you get the most out of our products and methodologies. In our case, the focus is on Front-End Design, hence the "FED"...
Posted to
Logic Design
(Weblog)
by
Team FED
on Tue, Mar 3 2009
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