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Extraction

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 2 2012
Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

A major advancement in 3D-IC through-silicon via (TSV) design will be unveiled Tuesday (Dec. 13) as representatives of CEA-LETI and ST-Ericsson describe the development of a three-die stack with wide I/O memory and logic. This tapeout is the result of a collaboration between these two organizations and...

Posted to Industry Insights (Weblog) by rgoering on Tue, Dec 13 2011
Re: Spectre simulation of calibre extracted layout

Hi, I know my problem now. it is what Andrew suggested. my circuit had several operating point. My suggestion is that you run DC analysis first to see if both schematic and post-layout simulation results match. if not, you can compare the netllist to find out the difference. sometimes, the schematic...

Posted to Custom IC Design (Forum) by whlinfei on Fri, Sep 16 2011
GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow

The design and manufacturing challenges of 20nm ICs are formidable, and will not be solved by loose collections of point tools. At the recent Global Technology Conference ( GTC ), Cadence presented its view of 20nm challenges and previewed a comprehensive 20nm design methodology that encompasses custom...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 7 2011
incorrect extraction issue

I am working with Virtuoso version IC6.1.3.500.13 and mentor 2011 (also have access to older versions and have previously used 2009). The pdk I am working with apparently has a known bug (confirmed by the foundry) such that the extracted transistors are always incorrect - instead of a 10 finger fet with...

Posted to Custom IC Design (Forum) by kristen on Fri, Aug 19 2011
Spectre simulation of calibre extracted layout

Hi, I am trying to make a calibre extraction of the R+C+CC parasitics and I am getting some strange results. The layout is DRC and LVS clean and when I extract the layout without parasitics, my simulations work well. When I extract C+CC it also works well, but then when I include the R parasitics, the...

Posted to Custom IC Design (Forum) by moralope on Thu, Apr 21 2011
New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

Cadence this week (Jan. 31) is announcing a "unified" 3D IC design methodology that drives creation, implementation, and verification across the digital, analog, and packaging domains. It's part of a larger announcement of a digital end-to-end flow. What follows are some more details on...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 31 2011
Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient

Digital designs are reaching 10's of millions of instances, which makes efficiency of the overall digital implementation and signoff flow critical to ensure predictability in the design schedule. A major stumbling block that can be a real threat to that predictability is iterations between different...

Posted to Digital Implementation (Weblog) by mikeNaustin on Wed, Mar 10 2010

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Extraction

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

Three Die Stack -- A Big Step “Up” for 3D-ICs with TSVs

Re: Spectre simulation of calibre extracted layout

GTC Presentation: Cadence Outlines Comprehensive 20nm Design Flow

incorrect extraction issue

Spectre simulation of calibre extracted layout

New Silicon Realization Design Methodology Boosts 3D ICs With TSVs

Signoff-Driven Implementation = Consistent and Convergent = Predictable and Efficient