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  • Dynamic Shape out of date, but not accessible.

    Hi All, I'm almost finished with my very first board layout using Allegro PCB editor 16.6 (latest hotfix June 2014), and I'm trying to generate the artwork so I can check over it and make sure it's good to send out to manufacturing. I'm having a problem when I try to create the artwork...
    Posted to PCB Design (Forum) by mwaskett on Tue, Jul 8 2014
  • Transient analysis error: "too few group members"

    Hello, I'm trying to run a transient analysis in ADE in Cadence to verify functionality of a digital circuit imported from a Synopsis flow, but I'm encountering the following errors: "Error happens when writting waveform for write error on PSF file" "Error happens when writing...
    Posted to Custom IC Design (Forum) by Phylosics on Fri, Apr 25 2014

    Sir, First of all, let me thank u for helping me in my project work, by giving valuble information. We are using BSIM-CMG (DG-MOSFET) model for circuit analyses and earlier, we were getting the output waveforms as well as pss analysis results by using virtuoso 6.1.4 version. But last day, the version...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Mar 4 2014
  • Unable to run PSS Analysis

    Sir, I have used BSIM-CMG107.0.0 Mosfet Compact model for my thesis work. But when I go for pss analysis, an error is shown saying that the behavioural file that you have given is not supported for pss analysis. The model is actually a verilog-A file. It would be grateful if you give me any solution...
    Posted to RF Design (Forum) by aravindkvarier on Tue, Feb 11 2014
  • STM065 536 Design Kit

    Hi, I am new with Cadence community I hope I get some help. I start to work on the STM065 536 design kit which support RFCMOS as well. I have a problems with the suitable model libraries that I should load in the ADE env in order to simulate some simple circuit, that for example has PMOS and NMOS of...
    Posted to RF Design (Forum) by paderborn on Fri, Jan 10 2014
  • Re: How to disable vr_axi checks

    You were close but the command is "set check" not "set_check". Here's an example from the examples directory, the file is VIPCAT11.30.007-s/vips/amba_axi/vr_axi/examples/sv/axi3/interface/vr_axi_test.sv: vr_axi::set_vip_cmd("set check \"...VR_AXI242...\" IGNORE"...
    Posted to Functional Verification (Forum) by StephenH on Mon, Jan 6 2014
  • Re: How to disable vr_axi checks

    Hi. This is done using the set_check() method, either at the start of the test, or even just during a part of the test, since you can switch the errors back on again if you wish. Here's a simple time-zero example. extend sys { run() is also { set_check("...ERR_VR_AXI190...",WARNING); /...
    Posted to Functional Verification (Forum) by StephenH on Fri, Jan 3 2014
  • Re: [Help]Issues regarding Extraction

    Hi Andrew, Thanks for your advice,Still I have some doubts... Tool version: cadence IC614,ASSURA410,MMSIM 101 I am using two scripts to invoke tool,in that certain variables are used to set lib paths.After invoking tool,Library viewer shows paths are valid and in that analogLib mapped into IC614.But...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • [Help]Issues regarding Extraction

    Hi Friends, I'm facing some issues while doing Extraction including inductances,like ERROR: Failed to find a cellview for (pinductor) ERROR: Failed to find a cellview for (pmind) ERROR: Failed to find a cellview for (vsource) ERROR: Failed to find a cellview for (ccvs) But its working properly for...
    Posted to RF Design (Forum) by hsps on Tue, Sep 10 2013
  • (IC6.1.5.500.12) ADE L messing up sim results(result access). Anyone familiar with that?

    Dear All, I've done extensive searching on forum for this, in vain. However, I am sure that someone else came across this, and maybe my search keywords weren't appropriate. If you know of thread relating to this, please point me to it. From time to time I get the those symptoms (they might all...
    Posted to RF Design (Forum) by ChrisXB on Fri, Jul 19 2013
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