Home > Community > Tags > Encouter Library Characterizer
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Encouter Library Characterizer

  • Encounter Library Characterizer gate recognition fails

    Dear all, I'm having a problem with the Encounter Library Characterizer tool in the ETS Suite. I'm trying to characterize standard cells, however, I'm having a problem that keeps returning at a lot of forums, but never seems to get solved. In the first step of characterization, the tool should...
    Posted to Digital Implementation (Forum) by HansRey on Wed, Jan 15 2014
  • Slotting problems

    Hi, 1. I was interested in knowing how can we slot wide metal connects in our automated flow of encounter, I have found an option in place and route, its a guide file which is a text file but that is an option which is not viable. 2. How can I increase the width of the routing metals. Thanks in advance...
    Posted to Digital Implementation (Forum) by BraveHeart on Mon, Jun 4 2012
  • ELC alf2vhdl error: Unexpected setuphold

    Halo, I've characterized a biphase enable flip flop with scan using ELC. The alf2vhdl command is unable to write out a VITAL Timing file for the flip flop, and gives the error as given in the thread title. This is very confusing since the alf2veri command writes out a verilog timing file with ease...
    Posted to Digital Implementation (Forum) by eklikeroomys on Wed, Sep 28 2011
  • ELC Simulation failed with status 512

    I am trying to create a standard cell library with transistor level model written in verilog A. I am getting the following output -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- Simulation Summary -*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- -------------+-------------+----------+------------...
    Posted to Digital Implementation (Forum) by rangha on Fri, Aug 19 2011
  • ELC library charachterization: db_prepare, gate file

    Hello, I am trying to characterize a bidirectional IO pad with a modified gate file using ELC 9.13. I don't get it run as described in the UG (gate file section, example BIO). I already had a look at the App Note, but still I have a few questions. If I do it as described in UG, I'll get "unknown...
    Posted to Digital Implementation (Forum) by scudex on Thu, Aug 11 2011
  • How we will Validate SDC??

    How we will consider weather that SDC file is suitable to our design or not ??
    Posted to Digital Implementation (Forum) by Ashok Nellore on Thu, Aug 4 2011
  • ELC - illegal "complementary" in gate file

    Hi all, I am trying to characterize a differential receiver using elc by using a gate model to specify the cell's behaviour. For the gate file, I copied the example given in the user guide, since its behaviour is the same as our custom cell: DESIGN (DIN); //PORT SECTION; INPUT P (P); INPUT N(N);...
    Posted to Digital Implementation (Forum) by MzQuarter on Sat, Jul 2 2011
  • Cadence ELC not recognising SPECTRE format

    Halo, I am using ELC to characterise a new standard cell library. I am using a SPECTRE .scs model file, but it seems that ELC is not recognising this file format correctly, as it complains about library and section declarations which are present in the model file. I assume that my command and/or elccfg...
    Posted to Digital Implementation (Forum) by eklikeroomys on Mon, May 16 2011
  • ELC memory macro characterization

    Hi All, I need some help for characterizing memory block generated by a memory compiler, which provides a spice model for the macro and a .lib file charatrized for nominal voltage. I am not really sure, how I can characterize a memory block with ELC. As I understand from the user guide, a gate file may...
    Posted to Digital Implementation (Forum) by amed on Tue, Apr 26 2011
  • ELC: liberty file output capacitance index different from simulation

    When generating a liberty dotlib for a bi-directional buffer, I have noticed that the cap index differs from what was used in the simulation. This only affects the PAD of the buffer and not the internal output. It appears to add the capacitance of the ouput pin(PAD) to the simulated value. Example: Using...
    Posted to Digital Implementation (Forum) by Brian Harrison on Tue, Oct 27 2009
Page 1 of 2 (11 items) 1 2 Next >