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Encounter,nanoroute encounter routing

  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • NanoRoute doesn't route multi height design

    Hello, as a test case I have a mixed design with 4 rows only. 3 standard core cell rows and 1 second row, that has a multiple of standard cell row height & pitch. Site definition is done properly. The design contains 2 cells only, one per each row. I created the floorplan, defined the globalNetConnect...
    Posted to Digital Implementation (Forum) by scudex on Wed, Feb 6 2013
  • RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

    I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...
    Posted to Custom IC Design (Forum) by eklikeroomys on Tue, Mar 15 2011
  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Nanoroute seems not to connect IO Pad pins to nets

    The problem I have is stated in the subject. I tracked this through a number of warnings at differnet phases in the flow. 1) The first trial route during pre-cts optimization issues the following warning: **WARN: (ENCTR-2325): 42 nets connect a pad term to a fterm without geometry and will not be routed...
    Posted to Digital Implementation (Forum) by kasyab on Thu, Oct 14 2010
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