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Encounter

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Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...

Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012
User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)

Clock concurrent optimization (CCOpt) is a new technology that runs clock tree synthesis (CTS) concurrently with physical optimization. It claims significant improvements in performance, power, and area - but the only way to really quantify such claims is through customer experience with real designs...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 23 2012
NRDB-51 warning

Hi All, I am having Warnings after CTS,Route and PostRoute opt WARNING (NRDB-51) SPECIAL_NET SG_rr is empty with no instance pin and special wire. Net with the same name will be routed but will not be connecte to the empty SPECIAL_NET. The SG_rr net is too long and having approx. 30ns net delay . By...

Posted to Digital Implementation (Forum) by gpremala on Thu, May 17 2012
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...

Posted to Mixed-Signal Design (Weblog) by paragb on Wed, May 16 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 2 2012
Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look...

Posted to Digital Implementation (Weblog) by Kari on Tue, May 1 2012
When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings...

Posted to Digital Implementation (Weblog) by wally1 on Thu, Apr 5 2012
User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)

Network processing chips are tough to design. They're big, they're fast, and they have to minimize power consumption. At CDNLive! Silicon Valley 2012 (the Cadence user group conference) Ranjit LoboPrabhu, physical design manager at Netronome Systems , shared some ways his company is going "green"...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 4 2012

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Encounter

Managing Inherited Connections with CPF in Virtuoso

User View: Broadcom Evaluates Clock Concurrent Optimization (CCOpt)

NRDB-51 warning

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

User View: Going “Green” With Low-Power Design and Clock Concurrent Optimization (CCOpt)