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Encounter,Techfile

  • Estimating Area & Power of RAM

    Hi, I have .lib file for a RAM and I am using 65nm technology library. I want to use this RAM with my design and calculate Area and Power, but when I syntheisize this RAM area report shows zero utilization. How can I obtain area in terms of number of gates for this RAM?. I like to know if it is possible...
    Posted to Digital Implementation (Forum) by dkhan on Fri, Jun 14 2013
  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Technology File Modification Issues / Encounter Prevent ViaCell Generation

    We are using the IBM cmrf8sf PDK. We have designed a standard cell library, but we were not able to import this into Abstract Generator because it lacked required metal spacing. To remedy this, we dumped the cmrf8sf techfile, added the required spacings, compiled it and attached to a library copy, and...
    Posted to Digital Implementation (Forum) by bsparkma on Tue, Jul 31 2012
  • RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

    I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...
    Posted to Custom IC Design (Forum) by eklikeroomys on Tue, Mar 15 2011
  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
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