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Encounter,Encounter ECO

  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • ENCOUNTER ECO - module

    Hi, we use encounter to implement most of our ECO's. However, we have an ECO which requires too many gates. We have heard that some people rip out a module, and have the tool replace the module with the new netlist. The question is what is the procedure to do that? It is easy enough to locate the...
    Posted to Digital Implementation (Forum) by checkerbum2 on Tue, Jun 26 2012
  • Slotting problems

    Hi, 1. I was interested in knowing how can we slot wide metal connects in our automated flow of encounter, I have found an option in place and route, its a guide file which is a text file but that is an option which is not viable. 2. How can I increase the width of the routing metals. Thanks in advance...
    Posted to Digital Implementation (Forum) by BraveHeart on Mon, Jun 4 2012
  • RULE LEF_DEFAULT definition for Abstract Generator/Encounter/NanoRoute

    I am using Cadence Abstract Generator to create abstract cell views for a standard cell library. In the Verify Step, I keep getting the following error: Encounter: (NRDB-158) There is no default via from LAYER MET1 to LAYER MET2 in RULE LEF_DEFAULT. I do not know how or where to define this RULE LEF_DEFAULT...
    Posted to Custom IC Design (Forum) by eklikeroomys on Tue, Mar 15 2011
  • Power Net Extraction Problem in Abstract Generator

    Halo, I am creating abstract cell views for a digital standard cell library using Cadence Abstract Generator.I have the following problem: In the Extract Step, I set the tool up to extract signal and power nets and to create pins on metal 1 so that my abstract view will keep its connectivity. The extract...
    Posted to Custom IC Design (Forum) by eklikeroomys on Mon, Mar 14 2011
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
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