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Encounter,EDI,silicon realization

  • Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers

    Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...
    Posted to Industry Insights (Weblog) by rgoering on Tue, Oct 18 2011
  • Why Cadence Bought Azuro – A Closer Look

    Cadence announced July 12 its acquisition of Azuro , a provider of "clock concurrent optimization technology" (ccopt). But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock...
    Posted to Industry Insights (Weblog) by rgoering on Sun, Jul 24 2011
  • 28 nm IC Design: The Devil Is In The Details

    Smaller process technologies are enticing chip makers with bigger rewards from their end products. The shorter gate lengths at 28nm promise faster transistor speeds and less leakage power, and can double the amount of the logic that can be put into the same die area. Most importantly, however, more die...
    Posted to Digital Implementation (Weblog) by Nora on Mon, Mar 14 2011
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