Home > Community > Tags > Encounter power routing/Power Routing using Encounter
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Cadence blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Encounter power routing,Power Routing using Encounter

  • Special routes with opens

    Hello everybody, I am working on floorplanning of a specific design with macro blocks (RAMs) and I have some issues : 1) My RAMs aren't connected to VDD/VSS 2) Number of Core ports routed: 0 open: 27478 Number of Followpin connections: 13739 3) When I make a verifyConnectivity, I have a message below...
    Posted to Digital Implementation (Forum) by Stewan on Wed, Jul 9 2014
  • Re: Short between IO filler blockage and IO pad pin

    To avoid shorts you have at least 2 ways: 1. If blockage represents actual wire in the filler (not pad ring) then shorts are valid and you need to resize pad pin in IO cell to meet spacing (maybe you need to consider width-depended spacing rules). 2. If blockage comes from pad ring wires in the fille...
    Posted to Digital Implementation (Forum) by mikhail on Wed, Apr 28 2010
  • missing vias in stacked power rings

    Hi all, we are working in a 5 metal layer process with Encounter 5.2. In our design, we have decided to stack the power rings, i.e. the VSS ring is on metal layer 1 and the VDD ring is in the same position but on metal layer 5. However, we are confronted with the following problem during power routing...
    Posted to Digital Implementation (Forum) by MMode on Thu, Nov 19 2009
  • Re: bottomup flow,how to make submodule ring and stripe can been see in top module

    I use : lefOut -stripePin -PGpinLayers 1 2 -extractBlockPGPinLayers 1 2 sub_block0.lef we do Sroute I add -stripeSCpinTarget boundaryWithPin option,since there are some space between my ring and block Boundary after load into toplevel ,I can see the power row/stripe pin come out is on Metal1 (lef/right...
    Posted to Digital Implementation (Forum) by verysmart on Tue, Sep 29 2009
  • Hard macros power routing issues

    Hello everybody, I import a design in SoC Encounter 7.1, where three hard macros (SRAMs) exist. The problem is that when I am trying to create the power stripes and connect them with the core rings to synthesize the power grid, the SRAM p/g pins cannot connect with the remaining power/ground network...
    Posted to Digital Implementation (Forum) by dbekiaris on Mon, Aug 3 2009
  • command to check vias on macros (RAMS)

    Hi can any body tell me, how do we ensure that vias are formed on macros. I mean is there any command or any way to check vias on Macros because checking for vias manually is a time taking work. Thanks suraj
    Posted to Digital Implementation (Forum) by surajece01 on Mon, Aug 3 2009
Page 1 of 1 (6 items)