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Encounter digital Implementation system
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Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory
No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look...
Posted to
Digital Implementation
(Weblog)
by
Kari
on Tue, May 1 2012
The Technology Behind Encounter 11.1 – Physical Aware Front End Design
In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Mar 6 2012
The Technology Behind Encounter 11.1 – Optimization for GHz, Giga-Gate, and 20nm Design
Realizing that high-performance (GHz range), high capacity (100M+ instances), and 20nm digital IC designs need new tools and methodologies, Cadence today (March 5, 2012) is announcing Encounter Digital Implementation System 11.1. Here's an inside look at three technology innovations that make it...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Mar 5 2012
ARM TechCon Paper: Early Architectural Planning With a Digital Implementation Flow
You might think that an IC digital implementation toolset, such as the Cadence Encounter Digital Implementation System, is only useful after RTL is developed and synthesized. But that's not necessarily the case. At the recent ARM TechCon conference, Cadence and Cisco Systems presented a flow that...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Nov 30 2011
Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers
Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 18 2011
Evolution of Design Exploration and Planning
The great architect Frank Lloyd Wright once said "you can fix it on the drafting board with an eraser, or on the construction site with a sledge hammer." The semiconductor design industry is a perfect example where finding issues later in the flow can be extremely expensive. Chips that fail...
Posted to
Digital Implementation
(Weblog)
by
abham
on Thu, Feb 17 2011
Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow
It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?" If the latter is your...
Posted to
Digital Implementation
(Weblog)
by
Design4Life
on Mon, Jan 31 2011
Encounter How To: Writing To/Reading From a File With TCL
A couple weeks ago, there was a good thread in the Digital Implementation Forums about managing buffering on nets between IOs and registers. The post touched on a number of interesting topics, but one of the fundamental building blocks I'd like to expand upon in this blog entry is the fundamental...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Wed, Feb 24 2010
Encounter Screencast: Editing Wires More Quickly With Bindkeys
The Encounter Digital Implementation System offers interactive wire editing capabilities via the Wire Editor. This is one part of the tool that becomes much easier to use with the help of a few bindkeys. In particular, I find the "Shift-S" bindkey useful in conjunction with "Auto Query"...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Thu, Jan 21 2010
Design Signoff Begins In Implementation
As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
Posted to
Digital Implementation
(Weblog)
by
PeteMc
on Wed, Jan 6 2010
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