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Encounter Timing System

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...

Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
Whatever Happened to Statistical Timing?

Several years ago, there was a lot of publicity about statistical timing analysis, which was thought by some to be the “next big thing” in IC design. Then things got quiet. But as process nodes head into the 45 nm and below territory, statistical static timing analysis (SSTA) may once again...

Posted to Industry Insights (Weblog) by rgoering on Thu, Apr 16 2009
How To Improve Timing Critical Path Analysis

By Jack Marshall Sr. Technical Leader Customer Solutions In my first article I wrote about how to generate a Global Timing Debug (GTD) timing report from within RC which would allow you to send all the necessary information to your favorite Cadence AE to facillitate their debugging of your critical timing...

Posted to Logic Design (Weblog) by Team FED on Tue, Apr 7 2009
Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"

Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen...

Posted to Digital Implementation (Weblog) by mikeNaustin on Fri, Mar 27 2009
Constraint Construction: What's Its Function? Part 3 of 4

Part 3. EXCEPTION PATHS: For Every Rule, There Is An Exception More often than not, I'll start an optimization on a block only to have it result in thousands of timing violations. Many times, the culprit is a missing path exception constraint. When you see timing violations that are suspicious, ask...

Posted to Digital Implementation (Weblog) by Thom Moore on Fri, Mar 6 2009
Enable Remote Timing Analysis Without Revealing Your RTL

By Jack Marshall Sr. Technical Leader Customer Solutions Team FED How would you like to send more than just a timing report to your favorite Cadence AE but you’ve got a proprietary design that can’t leave your company? What if there was a way to remotely enable more critical path analyses...

Posted to Logic Design (Weblog) by Team FED on Tue, Mar 3 2009
Constraint Construction: What's Its Function? Part 2 of 4

Part 2 - I/O TIMING: Talking Outside The Box It wouldn't be a chip or block if it didn't have to talk to something other than itself right? We could always assume that every input arrives at exactly the same time, and every output has exactly the same amount of external delay. The downside is...

Posted to Digital Implementation (Weblog) by Thom Moore on Wed, Feb 18 2009
Constraint Construction: What's Its Function? Part 1 of 4

Have you found yourself frustrated at the lack of some decent timing constraints? Perhaps made critical floorplanning and placement decisions only to have them thrown out because someone forgot to mention a tiny detail in the constraints? Often times, the role of timing constraints is marginalized until...

Posted to Digital Implementation (Weblog) by Thom Moore on Mon, Feb 9 2009
Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. And, the global credit crunch and economic recession has pulled the semiconductor industry down to the point of entering its eleventh recession. "I'm sorry it's happening," said US President George W. Bush...

Posted to Digital Implementation (Weblog) by RahulD on Wed, Dec 3 2008

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Encounter Timing System

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Design Signoff Begins In Implementation

Whatever Happened to Statistical Timing?

How To Improve Timing Critical Path Analysis

Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"

Constraint Construction: What's Its Function? Part 3 of 4

Enable Remote Timing Analysis Without Revealing Your RTL

Constraint Construction: What's Its Function? Part 2 of 4

Constraint Construction: What's Its Function? Part 1 of 4

Innovate Your Way Out of Recession With the New Encounter!