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Encounter Test

Videos, Presentations Highlight Front-End IC Design Methodologies

Want to know how other designers are solving front-end IC design challenges, and what Cadence R&D is doing to help? The Front-End Design (FED) Technology Summit, held at Cadence San Jose headquarters Dec. 6, 2012, provided some helpful answers. Presentations and videos from most of the sessions are...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 9 2013
difference between Random Resistance faults and deterministic faults?

what is random resistance faults? how different is it from the deterministic faults? why do we do the RRFA(random resistance fault analysis)?

Posted to Logic Design (Forum) by vipul982 on Tue, Jan 15 2013
How do I insert test point in the model?

the "analyze deterministic_faults" creates a test point insertion file in .dfa format. How do I further use this file to insert the test points in the design model?

Posted to Logic Design (Forum) by vipul982 on Tue, Jan 15 2013
test procedure in Cadence encounter test tool?

How do I write a test procedure in Cadence encounter test tool?

Posted to Logic Design (Forum) by vipul982 on Thu, Jan 10 2013
Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies about strategies they employed to overcome...

Posted to Logic Design (Weblog) by Kenneth Chang on Tue, Nov 27 2012
Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction except for some high-end CPU server and networking...

Posted to Industry Insights (Weblog) by rgoering on Thu, May 10 2012
Don’t Blow Up Your Chip on the Tester!

The photo at right shows a test socket and chip destroyed by thermal runaway. Can this really happen? Yes, it can and it sometimes does, if test power is significantly greater than functional power. To get a handle on this problem I talked to Bassilios Petrakis, product marketing director for Design...

Posted to Industry Insights (Weblog) by rgoering on Mon, Mar 26 2012
Design for Test (DFT) – New Challenges at Advanced Process Nodes

Design for test (DFT) doesn't get a lot of press these days, which is unfortunate, because the demands of DFT are dramatically increasing as designers move to smaller lithography nodes. New fault types, test compression, and faster automatic test pattern generation (ATPG) are becoming critical. To...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 15 2011
How Imec and Cadence “Wrapped Up” 3D-IC Test

One of the most challenging aspects of 3D-IC development involves the testing of vertical die stacks with through-silicon vias (TSVs). You have to propagate test data up and down through the stack, verify the functioning of TSVs that are too small to probe, and isolate the individual dies you want to...

Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 1 2011

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Encounter Test

Videos, Presentations Highlight Front-End IC Design Methodologies

difference between Random Resistance faults and deterministic faults?

How do I insert test point in the model?

test procedure in Cadence encounter test tool?

Register for Cadence's Front End Design User Summit -- December 6, 2012 in San Jose

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test

Don’t Blow Up Your Chip on the Tester!

Design for Test (DFT) – New Challenges at Advanced Process Nodes

How Imec and Cadence “Wrapped Up” 3D-IC Test