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Encounter Power System

Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types...

Posted to Digital Implementation (Weblog) by Kari on Fri, Feb 22 2013
Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership

A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Fri, Oct 19 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look...

Posted to Digital Implementation (Weblog) by Kari on Tue, May 1 2012
Webinar Report: Solving Mixed-Signal Power Grid Challenges

Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jan 11 2012
Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...

Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010
VoltageStorm Is Alive and Kicking!

If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is...

Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 27 2009

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Encounter Power System

Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells

Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

Webinar Report: Solving Mixed-Signal Power Grid Challenges

Design Signoff Begins In Implementation

VoltageStorm Is Alive and Kicking!