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Emulation

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products too fast. Users are looking at press releases and are wondering "sounds great, but does it really work?" Cadence announced earlier this week new in-circuit acceleration capabilities to our System Development...

Posted to System Design and Verification (Weblog) by fschirrmeister on Wed, May 16 2012
The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include accelerated VIP (AVIP). You may be wondering why Cadence is investing in accelerated VIP (which runs on an accelerated platform such as the Palladium XP) when we already have the market leading simulation VIP. Good question...

Posted to Functional Verification (Weblog) by PeteHeller on Tue, May 15 2012
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49 th DAC in San Francisco. Tuesday June 5 Addressing...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 14 2012
System-Level Low Power Design – What Will it Take to Move There?

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical...

Posted to Industry Insights (Weblog) by rgoering on Wed, Apr 18 2012
DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

Emulation and FPGA-based prototyping are becoming increasingly necessary for complex systems-on-chip, but where are these hardware-assisted tools going to come from? Should you invest the resources to build and maintain your own, or purchase a commercially available solution? In either case, what do...

Posted to Industry Insights (Weblog) by rgoering on Wed, Mar 7 2012
Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

DVCon, the premier conference for IC and systems verification, will be held Feb. 27- March 2 at the Doubletree Hotel in San Jose, California. This year's conference makes it clear that functional verification isn't just about digital RTL anymore. In fact, there's quite a bit of content in...

Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 30 2012
“Assertion Synthesis” Webinar: Questions, Answers About NextOp BugScope

You know a webinar is hot when the questions just keep rolling on in from the audience and go well into overtime. Such was the case in a newly archived Cadence webinar titled "Automate Assertion Generation for Simulation, Formal and Emulation Flows." The webinar showed how "assertion synthesis...

Posted to Industry Insights (Weblog) by rgoering on Mon, Oct 17 2011
Webinar: Easing the Pain of FPGA-Based Prototyping

Nearly every digital system-on-chip, ASIC or ASSP is prototyped in FPGAs, most typically for pre-silicon software development and debugging. The problem is that it can take months to get the prototype up and running with a functionally equivalent design. But there are easier ways to develop FPGA-based...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 8 2011
DAC Panel Calls Off “Battle” Between Prototyping and Emulation

A Design Automation Conference (DAC) panel June 8 looked like it was destined for controversy. It was titled, "Software-Hardware Verification Battle: Prototyping vs. Emulation." But that battle didn't happen. Instead, most participants agreed that several types of hardware/software integration...

Posted to Industry Insights (Weblog) by rgoering on Tue, Jun 14 2011
Q&A: A Closer Look at the Cadence Rapid Prototyping Platform

Cadence entered a new marketplace with the recent introduction of the Rapid Prototyping Platform , an FPGA-based prototyping environment that supports pre-silicon software development and system validation. The Rapid Prototyping Platform is part of the tightly integrated System Development Suite , which...

Posted to Industry Insights (Weblog) by rgoering on Wed, Jun 1 2011

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Emulation

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

The Facts: Why Accelerated VIP Is Needed for SoC Verification

Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges

System-Level Low Power Design – What Will it Take to Move There?

DVCon Panel Debate – “Build or Buy” Emulation and Prototyping?

Interested in Low Power, Mixed Signal, SystemC Verification? Here’s What to See at DVCon

“Assertion Synthesis” Webinar: Questions, Answers About NextOp BugScope

Webinar: Easing the Pain of FPGA-Based Prototyping

DAC Panel Calls Off “Battle” Between Prototyping and Emulation

Q&A: A Closer Look at the Cadence Rapid Prototyping Platform