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TSMC 2013 Symposium: Progress in 20nm, 16nm FinFET, and 3D-IC Technologies
The TSMC 2013 Technology Symposium , held April 9 in San Jose, California, brought good news for anyone interested in advanced node or 3D-IC technologies. Keynote speakers noted excellent yields and significant progress in 20nm planar, 16nm FinFET, and Chip-on-Wafer-on-Substrate (CoWoS) technologies...
Posted to
Industry Insights
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by
rgoering
on Sun, Apr 14 2013
Common Platform Forum Keynotes: 14nm FinFETs and Beyond
How far can we continue to scale semiconductors? 14nm FinFET technology is the next major move, but that's far from the end of the story, according to keynote speakers at the Common Platform Technology Forum in Santa Clara, California Feb. 5, 2013. The keynotes, still available for on-line viewing...
Posted to
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rgoering
on Wed, Feb 6 2013
ARM TechCon: Design at 14nm (or 10nm) – What’s Going to Change
The next semiconductor process node after 20nm promises tremendous power and performance benefits, but also poses some new challenges, according to a presentation by ARM and IBM at the ARM TechCon conference Oct. 30, 2012. The presentation showed how the "second generation" of double patterning...
Posted to
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rgoering
on Fri, Nov 2 2012
CDNLive! – IBM Expert Quantifies Design Impact of Double Patterning
Double patterning will be an essential lithographic technique for ICs at 20nm and below. The more we can understand it, and quantify its impacts on the design flow, the easier it will be to adopt. A good step towards that understanding was taken at CDNLive! Silicon Valley 2012 (the recent Cadence user...
Posted to
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rgoering
on Sun, Apr 1 2012
SPIE Papers Showcase DFM and Lithography R&D
Ten Cadence papers planned for the upcoming SPIE Advanced Lithography conference, set for Feb. 12-16 in San Jose, California, demonstrate recent R&D developments in both "design side" design for manufacturing (DFM) and the computational lithography that takes place during the manufacturing...
Posted to
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rgoering
on Thu, Jan 26 2012
GTC: GLOBALFOUNDRIES Charts Course for 28nm, 20nm and Beyond
The 28nm node is "fully enabled" and ready for production ramp-up, and 20nm early adopter flows are available now, according to GLOBALFOUNDRIES executives at the Global Technology Conference (GTC) in Santa Clara, California Aug. 30. In several morning sessions, speakers updated the company's...
Posted to
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rgoering
on Wed, Aug 31 2011
Video: Easing the Design Challenges of Double Patterning at 20nm
Double patterning lithography will be essential at 20nm and below until at least 2014, according to Lars Liebman, distinguished engineer at IBM. But it need not be a huge burden for engineers. In a talk at the Cadence booth at the Design Automation Conference in June, and newly available in the video...
Posted to
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rgoering
on Tue, Aug 23 2011
Flash Memory Summit: New Insights Into the Future of NAND Flash
With deployment in some 5 billion mobile devices worldwide, flash memory has been wildly successful. But where will nonvolatile memory technology go from here, and how much further can it scale? Some answers emerged from three keynote speeches at the Flash Memory Summit August 9. The speakers were Yoram...
Posted to
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rgoering
on Wed, Aug 10 2011
Common Platform Forum: A Clearer Path to Advanced Process Nodes
Insights into what you can expect at 32/28nm and below came to the forefront at the Common Platform Technology Forum Jan. 18, a well-attended one-day event in Silicon Valley. One point that caught my attention is that IBM is turning to a "gate last" high-k metal gate (HKMG) technology at 20nm...
Posted to
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by
rgoering
on Tue, Jan 18 2011
ARM Techcon: IBM Speaker Outlines Path to 22nm and Beyond
An IBM industry address at this week's ARM Technology Conference ( ARM Techcon ) included both inspiration and a warning. The inspiration came from optimistic descriptions of the technologies that will propel us to 22nm and below. The warning was that it takes at least 10 years to bring new silicon...
Posted to
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rgoering
on Wed, Nov 10 2010
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