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ETS

  • Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
    In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012

  • TimeDesign In ETS
    hi , Is there any command in ETS for getting timing summary (like timedesign in EDI). I need wns, tns, no: of violating paths for seup & hold and for all corners. - Bharath
    Posted to Digital Implementation (Forum) by bharat kurra on Thu, Apr 12 2012

  • Cell Delay
    In ETS I am getting the same cell delay for a cell BUF when I the design is set at 25C and 110C. Ideally I should see the delay increase. I saw the cell in the exactly same path in both the designs. What could be the explanation?
    Posted to Digital Implementation (Forum) by akshayd1 on Thu, Mar 15 2012

  • ELC alf2vhdl error: Unexpected setuphold
    Halo, I've characterized a biphase enable flip flop with scan using ELC. The alf2vhdl command is unable to write out a VITAL Timing file for the flip flop, and gives the error as given in the thread title. This is very confusing since the alf2veri command writes out a verilog timing file with ease...
    Posted to Digital Implementation (Forum) by eklikeroomys on Wed, Sep 28 2011

  • Re: SDF Errors
    Hi Scrivner, I have a situation similar to that of this thread. Some of our cells have sdf annotations unspecified in the verilog (giving a elaboration warning), but I also have missing sdf annotations requested in the verilog (thus leaving the default check values of 1 ns). I looked a bit but I'm...
    Posted to Digital Implementation (Forum) by MzQuarter on Thu, Aug 4 2011

  • Tortoise Versus Hare … or How to Improve Your Time to Tapeout Using In-Design Signoff
    Now that Wei Lii Tan has helped you with your New Year’s resolution to “create a chip that is so compelling …” in his previous blog , I would like to help you understand how Cadence is using our signoff qualified engines during the design implementation flow to reduce your time...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Feb 23 2011

  • Do Foundation Flows also exist for EPS or ETS?
    First post so please bear with me. We have seen posts, etc. about the encounter foundation flow. I have tried this and it works fairly well. Nice flow. While poking around in the ETS installation directory tree I found what appears to be foundation flows for EPS and ETS. Has anyone tried these either...
    Posted to Digital Implementation (Forum) by pdgeek on Tue, Oct 19 2010

  • Design Signoff Begins In Implementation
    As an ex-design engineer now working in EDA, I am often privileged to see advanced design methodologies from many of my customers. I would like to reflect on the recent trends that I am seeing around signoff analysis for digital ASIC designs. For the majority of ASIC designs, signoff analysis includes...
    Posted to Digital Implementation (Weblog) by PeteMc on Wed, Jan 6 2010

  • VoltageStorm Is Alive and Kicking!
    If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is...
    Posted to Digital Implementation (Weblog) by PeteMc on Mon, Apr 27 2009

  • Ideal net in ETS
    I have reset synchronizer at ip TOP whose output goes to reset/set pin of ALL the flop in my IP. I want to declare this net as an ideal net. How can I do this in ets? rtlcompiler by default considers all reset and clock nets as an ideal. But what about ets? Quite surprisingly, set_ideal_network is not...
    Posted to Logic Design (Forum) by Jaydip Mehta on Thu, Oct 16 2008
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