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  • Place and route on SOC encounter

    Hello, I am a newbie at place and route operation. Can anyone please tell me how do you make sure that all the blockes i your design are arranged in a certain way while doing place and route . I mean I have like around 300 odd blockes to be eranged and I want them to be ordered row wise and column wise...
    Posted to Digital Implementation (Forum) by amythpai on Sun, Mar 17 2013
  • Re: Doubt regarding SDF

    Thanks kari, But I have one doubt regarding this. I've used same max,min and typical lib for both encounter and ETS. So delay for each standard cells same in both encounter and ETS. Then Why we go for ETS to write sdf and timing optimization? If I'm wrong,correct me. Thanks, selvam.
    Posted to Digital Implementation (Forum) by selvam27 on Wed, Mar 13 2013
  • Via Placement issue.

    Hi every one, I'm Lakshmi Prashanth, and i'm new to this encounter tool, I've got a problem., initially when i was moving the PG net over the Macros, tool was automatically placing the via's, But suddenly yesterday, some via's are deleted automatically, I don't know how, and If...
    Posted to Digital Implementation (Forum) by Leader on Tue, Feb 12 2013
  • Cadence, ARM, Samsung 14nm Test Chip – Collaboration Eases FinFET Digital Implementation

    A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Jan 7 2013
  • Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New Signoff Approach

    In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Aug 6 2012
  • Doubt regarding SDF

    What is the difference between writing sdf from encounter and from ETS? I had written sdf(write_sdf) from encounter after postRoute and also write sdf(write_sdf) in ETS using spef generated by encounter. I have doubt that What is the difference between writing sdf from encounter and from ETS?
    Posted to Digital Implementation (Forum) by selvam27 on Fri, Jun 8 2012
  • Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

    In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
    Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
  • Problems Importing OA Design from Virtuoso into Encounter

    Hello, While trying to perform place and route using Encounter I'm "encountering" errors importing my design from Virtuoso. When I try to import the design, I get the following: Reading tech data from OA Library 'NCL' ... FE units: 0.001 microns/dbu, OA units: 0.001 microns/dbu...
    Posted to Digital Implementation (Forum) by TruLogic on Mon, Jan 10 2011
  • Do Foundation Flows also exist for EPS or ETS?

    First post so please bear with me. We have seen posts, etc. about the encounter foundation flow. I have tried this and it works fairly well. Nice flow. While poking around in the ETS installation directory tree I found what appears to be foundation flows for EPS and ETS. Has anyone tried these either...
    Posted to Digital Implementation (Forum) by pdgeek on Tue, Oct 19 2010
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