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ESL,verification

Why Virtual Platforms Need Advanced Verification

By allowing software development long before silicon is available, virtual platforms (also known as "virtual prototypes" or simply "simulation") are playing an increasingly important role in electronic system development. But they're just an initial step in the next generation...

Posted to Industry Insights (Weblog) by rgoering on Thu, Sep 23 2010
Webinar: Some Practical Advice on Adopting ESL

Changing design methodologies is much like changing the engine of a jet airplane mid-flight, according to David Black, ESL practice lead at XtremeEDA . So what's the best way to step up to electronic system level (ESL) design? The key is developing the right models for the right users, Black said...

Posted to Industry Insights (Weblog) by rgoering on Wed, Sep 15 2010
Can Agile Software Development Methods Help SoC Design?

Are you looking for an easier way to develop the right product for your target customer, on time and within budget? Perhaps it's time to learn something from the software world and apply "agile" software development methods to SoC design, according to Neil Johnson, principal consultant...

Posted to Industry Insights (Weblog) by rgoering on Wed, Aug 18 2010
Imperas Interview: Connecting Virtual Platforms To HW/SW Verification

Imperas is a provider of virtual platform technology and a member of the new Cadence System Realization Alliance . Imperas has also been doing some interesting work with Cadence that involves the integration of virtual platform models with Incisive simulation and Incisive Software Extensions . Simon...

Posted to Industry Insights (Weblog) by rgoering on Thu, Aug 12 2010
System Realization Alliance -- An Industry Collaboration

System Realization is a very broad topic. It encompasses all aspects of system design, from chips to chassis. In particular, innovations in software are driving changes in the value chain, as highlighted in the EDA360 industry vision document . In order to foster industry innovation and ease customer...

Posted to System Design and Verification (Weblog) by Steve Brown on Wed, Jul 21 2010
Cadence Contributes ESL Methodology To TSMC Reference Flow 11

The EDA360 industry vision document shows how growing complexity and application-driven development are requiring orders-of-magnitude improvements in design productivity. With its new Reference Flow 11 , TSMC has taken an important step towards a standard approach that will help customers develop software...

Posted to System Design and Verification (Weblog) by Steve Brown on Fri, Jun 11 2010
Synopsys’ “Synphony” Announcement – Welcome to the Party!

I’m glad Synopsys realized the world really IS moving to the next higher level of abstraction above RTL and now the party can really get started! It’s great for RTL designers, for their companies, and the EDA industry. With the huge productivity boost that'll come from working at a higher...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Wed, Oct 14 2009
SystemC Debug: A Summary of Summary Probes

SystemC goes well beyond generic C and C++ to provide a number of semantic constructs that are essential for system-level modeling, design and verification. Among the most powerful of these are threading and concurrency. Using threading is required in order to represent concurrent systems, whether for...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, May 15 2009

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ESL,verification

Why Virtual Platforms Need Advanced Verification

Webinar: Some Practical Advice on Adopting ESL

Can Agile Software Development Methods Help SoC Design?

Imperas Interview: Connecting Virtual Platforms To HW/SW Verification

System Realization Alliance -- An Industry Collaboration

Cadence Contributes ESL Methodology To TSMC Reference Flow 11

Synopsys’ “Synphony” Announcement – Welcome to the Party!

SystemC Debug: A Summary of Summary Probes