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ESL,C-to-Silicon,System Design and Verification

TLM Design and Verification: What to See at DAC This Year

If you are attending the Design Automation Conference ( DAC 2012 ) June 4-7 in San Francisco and you are interested in SystemC/TLM driven design and verification, including high-level synthesis, there are a lot of interesting sessions. First, there is a parallel conference going on Saturday and Sunday...

Posted to System Design and Verification (Weblog) by Jack Erickson on Thu, May 31 2012
Methodology Is Important But Language Matters - Part 1

Historical trends in languages Many of us have traveled around the world, and while we can often communicate with local people in our own language, we realize it is best to communicate using the local language. It helps to "break the ice" if you at least try to use some of the local language...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Jan 26 2010
The Golden Age of Electronics

About a month ago I took my family to The Bakken Museum in Minneapolis, Minnesota. We wanted to visit the museum for some time, but never made quite it. We even went there once last year only to find out it is closed every Monday. The history of the museum derives from from Earl Bakken, a co-founder...

Posted to System Design and Verification (Weblog) by jasona on Fri, Jun 26 2009
System-level Low Power Techtorials/Workshops Off To A Great Start!

Back in my 24 March blog I mentioned how Cadence was kicking off a major techtorial/workshop series across North America on low power chip design, using the newest Cadence tools at the ESL/System/Chip Architecture level. Last week we concluded the first three events, all in California: Irvine, San Diego...

Posted to System Design and Verification (Weblog) by SteveSvoboda on Mon, Apr 20 2009
C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis tool. The question is usually based on the fact that SystemC is the input language for CtoS. It is partially correct. In reality, CtoS is both a High and a Low level synthesis tool. On the High Level side...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, Apr 3 2009
C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other ESL tools is its ability to make incremental changes to the generated RTL based on very small changes to the System C source code. This capability, allows designers to make very small changes to the generated RTL and gate...

Posted to System Design and Verification (Weblog) by TeamESL on Thu, Mar 19 2009
Reflections on ESL: Where Are We and Where We Are Going

Many of the messages published by Gabe Moretti in his recent EETimes article resonate very well with Cadence strategy. Specifically: Evolving standards are important with SystemC and TLM becoming the center of the ESL world Cadence supports SystemC with its Incisive Enterprise Simulator and C-to-Silicon...

Posted to System Design and Verification (Weblog) by Ran Avinun on Tue, Feb 24 2009
C-to-Silicon Does Not Require a Library Characterization

One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis tools is its ability to directly read industry standards .lib files. By providing this ability an expensive library characterization which is required by other ESL Synthesis tools is avoided. This approach not only avoids...

Posted to System Design and Verification (Weblog) by TeamESL on Fri, Feb 13 2009
New Blog series- Team ESL

Cadence is well known for its leadership in system verification leveraging its HW-assisted verification market segment. Last year, we have expanded this segment offering, combined it with our System Software capabilities (focusing on Electronic System Level - ESL) into a larger segment - System Design...

Posted to System Design and Verification (Weblog) by Ran Avinun on Fri, Feb 13 2009

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ESL,C-to-Silicon,System Design and Verification

TLM Design and Verification: What to See at DAC This Year

Methodology Is Important But Language Matters - Part 1

The Golden Age of Electronics

System-level Low Power Techtorials/Workshops Off To A Great Start!

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

Reflections on ESL: Where Are We and Where We Are Going

C-to-Silicon Does Not Require a Library Characterization

New Blog series- Team ESL