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EE Times,Tensilica

  • IP Cores: How to Get There from Here

    Every time I look at the ITRS roadmap I get a little queasy. In five years, the average design is supposed to have twice the number of logic gates alone (north of 300 million). At the same time, we're supposed to double design productivity (and, presumably churn out more complex ICs because the world...
    Posted to The Fuller View (Weblog) by Brian Fuller on Fri, Oct 11 2013
  • Right Turn on Seely Avenue -- A New Blog from Brian Fuller

    Years ago (and by years ago I mean so far back there’s no digital record of it), I wrote an EE Times column about a legal dispute involving Cadence. I think it had a high-and-mighty tone to it, and I used the words “moral” or “morality” probably a little too liberally. Cadence...
    Posted to The Fuller View (Weblog) by Brian Fuller on Thu, May 30 2013
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