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EDN
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IP Cannot be an Efficient Abstraction Level Without SystemC!
EDN recently featured a lengthy article entitled " SOCs: IP is the new abstraction. Reusable IP, not system-level language, has become the new level of abstraction ." The point of view is that SoC design now is such a large undertaking that the best way to efficiently design one is to assemble...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Fri, Aug 12 2011
Cadence’s Steve Leibson Launches EDA360 Insider Blog
Last April Cadence published the EDA360 vision paper , a document that outlines a new, application-driven approach to electronic system design. From the start it was a vision for the entire EDA industry, not just Cadence. And it soon became clear that the paper was not just about EDA, but about a major...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Sep 28 2010
The Cadence ESL Machine Keeps Building Momentum!
Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon Compiler (a finalist) received two write-ups in www.deepchip.com . One of the write-ups is by Gernot Koch of Micronas who evaluated CtoS last fall. I checked with the CtoS AEs who supported Gernot and his team, and...
Posted to
System Design and Verification
(Weblog)
by
SteveSvoboda
on Fri, Apr 17 2009
EDN's 19th Annual Innovation Awards
Two of Cadence system D&V products have been selected as the finalists for the EDN innovation award : Palladium DPA (Dynamic Power Analysis) and C-to-Silicon Compiler . I went to the award Dinner this week. In the entrance, I have met Ron Wilson who told me that he believes in the current economic...
Posted to
System Design and Verification
(Weblog)
by
Ran Avinun
on Fri, Apr 3 2009
Great Article by Freescale: Timing Convergence Accross the Flow is "Very Important"
Having consistency and correlation in timing analysis across the design flow is "very important" according to Freescale Semiconductor's Shruti Rakheja and Naveen Sampath Krishna in a recent Electronic Design News (EDN) article and I'm sure most of you would agree. As stated by Naveen...
Posted to
Digital Implementation
(Weblog)
by
mikeNaustin
on Fri, Mar 27 2009
Accurately Measuring Power
I was browsing low power news the other day, and came across an interesting announcement from AMD regarding some new processors being released. http://news.cnet.com/8301-1001_3-10149696-92.html. These are follow up processors to their Shanghai core series. AMD has released both an energy efficient HE...
Posted to
Logic Design
(Weblog)
by
Rich Owen
on Mon, Feb 9 2009
Re: .* file extensions ...
The dbk is the last saved back up of the dsn file. The DSNlck is a locked DSN file.
Posted to
IC Packaging and SiP Design
(Forum)
by
Amritapuri
on Sat, Nov 22 2008
EDN blogger talks about Allegro 16.2 release
Of interest to readers of this forum. An EDN blogger today talks about our SPB 16.2 release. “Cadence is underlining the observation that no longer can we regard PCB design as somehow a simple process, and package design as a mechanical problem,” writes EDN executive Editor Ron Wilson. “With...
Posted to
IC Packaging and SiP Design
(Forum)
by
Dieds
on Mon, Aug 18 2008
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