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EDI

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis, Test and Verification Flow were born! What is a RAK...

Posted to Logic Design (Weblog) by SumeetAggarwal on Tue, Jul 24 2012
Capturing and Processing Encounter Console Output with "redirect"

In my last post I wrote about writing more compact db access scripts with dbGet's expression-based matching . We found all of the high fanout nets in the design which weren't clock nets: dbGet [dbGet top.nets {.numInputTerms > 16 && .isClock == 0}].name This writes the name of each...

Posted to Digital Implementation (Weblog) by BobD on Mon, Jul 23 2012
ENCOPT-3175 ---> warning?

I am seeing below errors as well.. **WARN: (ENCOPT-3175): Break cycle @ [-1 -1 15] **WARN: (ENCOPT-3161): Cannot find node to be deleted. **WARN: (ENCOPT-3175): Break cycle @ [-1 -1 15] **WARN: (ENCOPT-3161): Cannot find node to be deleted.

Posted to Digital Implementation (Forum) by anil chatrathi on Fri, Jul 6 2012
How to coonect two std cell pins logically in EDI

Hi All, I have to connect inst1/A ----> inst1/B A--> n1 B --> n2 How do I remove the previos connection and make a new connection? Regards, Anil

Posted to Digital Implementation (Forum) by anil chatrathi on Tue, Jun 12 2012
Writing More Compact Encounter Scripts with dbGet Expressions

Querying the Encounter database with dbGet is typically pretty concise to begin with. But you might not be aware of its support for expression-based matching, which enables even more compact scripting. Let's take a very simple but common scripting challenge: Finding all of the high fanout nets in...

Posted to Digital Implementation (Weblog) by BobD on Wed, May 30 2012
Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist...

Posted to Mixed-Signal Design (Weblog) by AndreasLenz on Wed, May 23 2012
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...

Posted to Mixed-Signal Design (Weblog) by paragb on Wed, May 16 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...

Posted to Industry Insights (Weblog) by rgoering on Mon, May 7 2012
Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

No matter how you run your power analysis - with Encounter Power System (EPS) or from within Encounter Digital Implementation (EDI) System - you're probably familiar with the result directory. It will look something like VDD_125C_avg_1 and have lots of files inside. The first ones you probably look...

Posted to Digital Implementation (Weblog) by Kari on Tue, May 1 2012
When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows

Maximizing the usage of Multi-cut vias by the router is one key to improving yield. And at advanced nodes it is essential step in the flow. So what are the proper settings and flow to use to maximize multi-cut via insertion with NanoRoute? And how do I know if I'm using the latest recommended settings...

Posted to Digital Implementation (Weblog) by wally1 on Thu, Apr 5 2012

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EDI

Boost Productivity With Synthesis, Test and Verification Flow Rapid Adoption Kits (RAKs)

Capturing and Processing Encounter Console Output with "redirect"

ENCOPT-3175 ---> warning?

How to coonect two std cell pins logically in EDI

Writing More Compact Encounter Scripts with dbGet Expressions

Managing Inherited Connections with CPF in Virtuoso

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Directory

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi-cut Via Insertion Flows