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EDI

Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality

If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation March 12, 2013, given by Jack Benzel (right), expert...

Posted to Industry Insights (Weblog) by rgoering on Wed, May 1 2013
Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

3D-IC technology has gone from the "grandiose plans" of several years ago to the "practical issues" of ramping up for widespread deployment, according to one panelist at the Electronic Design Process Symposium (EDPS) April 18, 2013 in Monterey, California. That's a pretty good...

Posted to Industry Insights (Weblog) by rgoering on Tue, Apr 23 2013
Multi-Level Physical Hierarchical Flow – A New Approach for Giga-Scale ASIC Design

A presentation at the DesignCon 2013 conference illustrated a new methodology that speeds timing closure for ASIC and SoC designs with hundreds of millions of gates. Called "multi-level physical hierarchy design," it overcomes many limitations of conventional "two level" hierarchical...

Posted to Industry Insights (Weblog) by rgoering on Mon, Apr 1 2013
Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

At CDNLive-Silicon Valley this year, we had an excellent mixed-signal track for two days. Cadence customers including IBM, Texas Instruments, Maxim and Freescale shared their mixed-signal methodologies and tricks with the Cadence design community. The key challenges that our mixed-signal customers face...

Posted to Mixed-Signal Design (Weblog) by Sathish Bala on Fri, Mar 29 2013
Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis

When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use a perl script to filter out the pwr/gnd bumps and...

Posted to Digital Implementation (Weblog) by Kari on Tue, Mar 26 2013
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?

Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...

Posted to Digital Implementation (Weblog) by Vasu Madabushi on Sun, Mar 10 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...

Posted to Industry Insights (Weblog) by rgoering on Tue, Feb 12 2013
Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation (EDI) System

Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to achieve this, knowing that manual power optimization...

Posted to Digital Implementation (Weblog) by MJ Cad on Tue, Feb 12 2013
NanoRoute doesn't route multi height design

Hello, as a test case I have a mixed design with 4 rows only. 3 standard core cell rows and 1 second row, that has a multiple of standard cell row height & pitch. Site definition is done properly. The design contains 2 cells only, one per each row. I created the floorplan, defined the globalNetConnect...

Posted to Digital Implementation (Forum) by scudex on Wed, Feb 6 2013
RTL Compiler Hierarchical Flow

Hello, Please, which is the manual that I must read to obatin the information on how to perform the hierarchical flow for RTL compiler synthesis ? Regards, Vitorio.

Posted to Logic Design (Forum) by lvcargnini on Tue, Feb 5 2013

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EDI

Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality

Panel: 3D-IC Design Experts Tackle “Practical Issues” in 2.5D and 3D TSV Deployment

Multi-Level Physical Hierarchical Flow – A New Approach for Giga-Scale ASIC Design

Unleashing Mixed-Signal Tech on Tours (ToTs) in North America

Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis

CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?

10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions

Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation (EDI) System

NanoRoute doesn't route multi height design

RTL Compiler Hierarchical Flow