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CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?
Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking...
Posted to
Digital Implementation
(Weblog)
by
Vasu Madabushi
on Sun, Mar 10 2013
10nm and 14nm FinFETs Pose Challenges – But Collaboration Brings Solutions
10nm and 14nm FinFET design will have a lot of challenges, but collaboration among semiconductor ecosystem partners is finding solutions, according to a presentation given at the Common Platform Technology Forum Feb. 5, 2013. The presentation was given by Vassilios Gerousis (right), distinguished engineer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Feb 12 2013
Mixed Signal Technology Summit Proceedings Now Available
In September 2012, Cadence held its second Mixed-Signal Summit in San Jose, California. 150 users attended the Summit. The full day program was packed by user presentations. Strong participation and attendance was yet another confirmation of increased design activities in the mixed-signal area. Attendees...
Posted to
Mixed-Signal Design
(Weblog)
by
nizic
on Thu, Dec 13 2012
Cadence Has Significant Presence in ARM TechCon 2012 and Worldwide ARM Technical Symposiums
The recently concluded ARM TechCon 2012 , the annual event for ARM users (including hardware and software engineers) along with ARM ecosystem partners, was a huge success. Once again, this event showcased the excellent Cadence-ARM partnership that's helping to bring next generation electronic designs...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Wed, Nov 14 2012
Press Release About TSMC Flow, Blog from ARM Validate Cadence’s Mixed-Signal and 20nm Leadership
A press release and a blog post caught my attention this week (October 15, 2012), and they have clearly demonstrated Cadence's leadership in 20nm process nodes and mixed-signal solutions. The press release is titled " TSMC Selects Cadence Virtuoso and Encounter Platforms for its 20nm Design...
Posted to
Mixed-Signal Design
(Weblog)
by
Sathish Bala
on Fri, Oct 19 2012
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, May 7 2012
Cadence-ARM Collaboration Brings Optimized Tools to SoC Designers
Cadence and ARM have been working closely together for several years, and that relationship reached a new milestone Oct. 18 with the joint announcement of the first 20nm tapeout using the Cortex-A15 MPCore processor. The announcement also brought news of a multi-year technology collaboration that will...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Oct 18 2011
Why Cadence Bought Azuro – A Closer Look
Cadence announced July 12 its acquisition of Azuro , a provider of "clock concurrent optimization technology" (ccopt). But why, given that Cadence already has clock tree synthesis inside the Encounter Digital Implementation Platform? The answer is that Azuro technology goes far beyond clock...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Sun, Jul 24 2011
Page 1 of 1 (8 items)