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EDA,SystemVerilog

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year

Great news.... Incisive Debug Analyzer (IDA) is one of five finalists for the EETimes/EDN Annual Creativity in Electronics (ACE) Awards in the Software Product of the Year category. In addition to IDA, Lip-Bu Tan and Cadence are also finalists for ACE Executive of the Year and Company of the Year, respectively...

Posted to Functional Verification (Weblog) by Karnane on Mon, Mar 25 2013
IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

EDA standards are a crucial enabler of today's complex electronic design flows - and it takes a lot of hard work to create them. Few know this better than Stan Krolikoski, who got involved with VHDL standardization in the early 1980s and has taken a leadership role in standards development ever since...

Posted to Industry Insights (Weblog) by rgoering on Mon, Dec 3 2012
Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a tool crash. In Specman you would usually see something like: *** Error: OS signal 11 (segmentation violation) received See the stack trace in ./specman.err To debug: --------- o Rerun the same test with the same seed in...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Apr 17 2012
Support for e Language Macros in Amiq DVT Tool

DVT ( D esign and V erification T ools), a product offering from a 3rd party vendor, AMIQ , is for verification engineers working with e and SystemVerilog who are dissatisfied with the limitations of plain text editors and plain text searches (grep) when reading, writing or understanding source code...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 25 2011
Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

A recent customer blog interview with Geoffrey Faurie from ST Microelectronics and Richard Goering from Cadence was posted on Cadence.com with the title: " Is e or SystemVerilog Best for Constrained-Random Verification? " This blog post has received much positive feedback from other Specman...

Posted to Functional Verification (Weblog) by teamspecman on Tue, Jan 18 2011
Users Employ Specman Constrained-Random Verification for Complex IP

Two recent customer examples have shown the effectiveness of Specman constrained-random verification for complex SoCs. Raimund Soenning, manager of hardware development for the Graphics Competence Center at Fujitsu Semiconductor Europe (Germany), and Sarmad Dahir, ASIC designer at Ericsson (Sweden),...

Posted to Functional Verification (Weblog) by teamspecman on Fri, Sep 3 2010
A Look Back On 2009 (Before Hazarding Predictions For 2010)

Before I gaze into a crystal ball and add to the many fine predictions already made for the remaining 11/12ths of 2010 (articles by my colleagues Jack Erickson and Richard Goering are my favorites so far); allow me to review my 2009 predictions against the main verification technology-specific observations...

Posted to Functional Verification (Weblog) by jvh3 on Thu, Jan 28 2010

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EDA,SystemVerilog

Incisive Debug Analyzer is a Finalist for EETimes and EDN ACE Software Product of the Year

IEEE Award Honors Stan Krolikoski as EDA Standards Pioneer

Analyzing Error Reports When Specman Crashes

Support for e Language Macros in Amiq DVT Tool

Specman/e Users Voice Their Opinions on Benefits of e over SystemVerilog

Users Employ Specman Constrained-Random Verification for Complex IP

A Look Back On 2009 (Before Hazarding Predictions For 2010)