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  • User Interview: How ECO Handling Works With Equivalence Checking

    Vishvabhusan Pati is a senior staff engineer and manager at Qualcomm , where he’s involved in design work and formal and semi-formal design verification. In this Q&A interview, he discusses advantages and limitations of formal equivalence checking, and describes his experience with automated...
    Posted to Industry Insights (Weblog) by rgoering on Thu, Nov 19 2009
  • User Panel: Can Formal Tools Reduce Need For Simulation?

    It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort. What I found interesting was the amount of discussion...
    Posted to Industry Insights (Weblog) by rgoering on Mon, Nov 16 2009
  • How-to Plans for ECOs - Advice From Experts

    By Bassilios Petrakis I often wonder whether designers plan out well in advance their ECO methodology and strategy for a project. For instance, how do they determine how many spare gates to add, what type, where to place them, how to connect them. Or, what is the impact of RTL coding style, aggressive...
    Posted to Logic Design (Weblog) by Team FED on Thu, Oct 15 2009
  • Friday Fun: A Last-minute ECO

    In this week's episode, the Dante Semi team is about to tape out when they get a last minute spec adjustment from their primary customer. Does this sound familiar? How will they make the change and verify it quickly enough to be able to tape out on time? (Hint: Conformal ECO ). Enjoy! If video fails...
    Posted to Logic Design (Weblog) by Jack Erickson on Fri, Sep 4 2009
  • C-to-Silicon Compiler Is The Only ESL Tool With ECO Capabilities

    Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to other ESL tools is its ability to make incremental changes to the generated RTL based on very small changes to the System C source code. This capability, allows designers to make very small changes to the generated RTL and gate...
    Posted to System Design and Verification (Weblog) by TeamESL on Thu, Mar 19 2009
  • Tapeout!

    With an early December tapeout looming, I've found myself too busy to write a post this week. But then I thought, "Why not write about tapeout?". Here are some things I try to do during a project so that those last few weeks before a deadline are as stress-free as possible: Run an early...
    Posted to Digital Implementation (Weblog) by Kari on Thu, Nov 20 2008
  • Anyone know an easy way to do a WAS/IS type report?

    Hey all, I have a design in progress where I am constantly updating the schematic with new parts or value changes. Our project managment team like to get was/is type reports for the changes... So if I replace U21 with a different IC, the report would reflect that. I know that design differences has this...
    Posted to PCB Design (Forum) by QSCMatt on Thu, Nov 6 2008
  • Re: Is this eco design flow right?

    Hi I want to learn ECOplace capability of Encounter. Specifically, I have a design, (and a netlist, a def etc) (a). I save the entire (original) design "SaveDesign... " (b). I now have a modified .v nelist. (c). From here on, I want to place the additional logic in the modified.v netlist into...
    Posted to Digital Implementation (Forum) by Sirrius on Tue, Oct 28 2008
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