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ECO
16.2
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12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs
The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react...
Posted to
Mixed-Signal Design
(Weblog)
by
paragb
on Wed, May 16 2012
Managing ECOs in Mixed Signal Designs
Imagine you are days away from completing the implementation of a fairly complex mixed-signal design, and you are already day-dreaming about the vacation you have planned in a few weeks. Then it happens -- the dreaded change in the design requiring ECOs to digital or analog content, or worse yet, implementation...
Posted to
Mixed-Signal Design
(Weblog)
by
Benatcdn
on Thu, Sep 29 2011
spare logic is not tied up/down properly after ECO route
In my ECO step, a number of logic gates are freed up and become spare gates. They should be connected to VDD or GND selectively. What command should I use? The large majority are grounded, but a few are tied high. Note: I don't have tieHi or tieLo cells in my library; I want to hook up directly....
Posted to
Digital Implementation
(Forum)
by
achilles
on Fri, Jun 17 2011
System Development Suite - Connecting Software to Hardware Design and Verification
I've been at CDNLive! EMEA watching demos of the newly announced System Development suite, and it's mindblowing. I'm seeing good old ncsim running Android interactively on the Virtual System Platform. You open an app in the virtual Android interface and you can stop the software, or even...
Posted to
System Design and Verification
(Weblog)
by
Jack Erickson
on Mon, May 9 2011
Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help
Early adopters are starting to design at 28nm and are running into some challenges, according to Rahul Deokar, product management director for digital Silicon Realization at Cadence. In this interview he talks about challenges designers are experiencing due to design rules, lithography, low power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 16 2011
Going 'Digital End-to-End' ... and Riding Your ECOs to the Finish Line
Thinking of your next ASIC ECOs? It could be for today, or maybe you are considering your next ASIC ECO methodology. You are probably not alone ... most designs will go through ECOs , whether they are related to bug fixes (those 'oh oh' moments of silence), or intended functional changes (which...
Posted to
Logic Design
(Weblog)
by
Kenneth Chang
on Mon, Feb 7 2011
Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End Flow
It hasn't been that long, but do you recall your new year's resolution? Eat healthier? Have more work-life balance? Exercise more? Or, what about, "create a chip that is so compelling and useful, it blows everybody's socks off in the semiconductor industry?" If the latter is your...
Posted to
Digital Implementation
(Weblog)
by
Design4Life
on Mon, Jan 31 2011
User Interview: How Metal-Only ECOs Save Full Silicon Respins
As anyone who has been through the process knows, a complete (all layer) silicon respin is extremely time-consuming and costly. At the recent CDNLive! Silicon Valley, Ranjit LoboPrabhu, back-end lead implementation engineer at Netronome , discussed a better approach. In a paper co-authored with Bob Dwyer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 23 2010
Encounter 101: Implementing ECOs with ecoDesign
When people say "ECO" in the context of back-end digital implementation tools, they can mean a number of things: TCL commands that trigger netlist changes to the design Functionality that takes RTL-based changes and automatically implements them automatically and surgically Functionality that...
Posted to
Digital Implementation
(Weblog)
by
BobD
on Tue, Sep 14 2010
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