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ECO,Industry Insights
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Why Multi-Mode, Multi-Corner (MMMC) ECO Closure Requires a New Signoff Approach
In the semiconductor design flow, engineering change orders (ECOs) are as inevitable as death and taxes. While this has always been the case, ECO timing closure is becoming increasingly difficult as the number of operating modes and process-voltage- temperature (PVT) corners skyrockets. What's needed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Aug 6 2012
High-Level Synthesis Users: Productivity Gains Beckon, But Learning Curve Comes First
SystemC-based high-level synthesis (HLS) tools have greatly improved in recent years and are undergoing adoption by many large semiconductor companies. But to get high productivity out of HLS, current RTL designers will first face a learning curve, according to panelists at the recent Design Automation...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Jun 25 2012
12 Hot EDA Topics – 78 DAC Demo Sessions
Whatever your role in the chip or system design process, there is probably a Cadence demo geared to your interests at the Design Automation Conference ( DAC 2012 ) June 3-7 in San Francisco. Cadence has three demo suites at its booth (#1930) and is running one-hour demos from 10:00 am to 5:00 pm Monday...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, May 24 2012
Q&A: What Designers are Finding at 28nm – and How a “Unified” Digital Flow Can Help
Early adopters are starting to design at 28nm and are running into some challenges, according to Rahul Deokar, product management director for digital Silicon Realization at Cadence. In this interview he talks about challenges designers are experiencing due to design rules, lithography, low power, mixed...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Feb 16 2011
User Interview: How Metal-Only ECOs Save Full Silicon Respins
As anyone who has been through the process knows, a complete (all layer) silicon respin is extremely time-consuming and costly. At the recent CDNLive! Silicon Valley, Ranjit LoboPrabhu, back-end lead implementation engineer at Netronome , discussed a better approach. In a paper co-authored with Bob Dwyer...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Tue, Nov 23 2010
Q&A: What Cadence Has Learned About High Level Synthesis
With the recent release of Cadence C-to-Silicon Compiler, Cadence has joined the rapidly growing high-level synthesis (HLS) marketplace. In this interview Mike "Mac" McNamara, vice president and general manager of the Cadence Systems Software Group, talks about what Cadence has discovered about...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Wed, Mar 24 2010
User Interview: How ECO Handling Works With Equivalence Checking
Vishvabhusan Pati is a senior staff engineer and manager at Qualcomm , where he’s involved in design work and formal and semi-formal design verification. In this Q&A interview, he discusses advantages and limitations of formal equivalence checking, and describes his experience with automated...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Thu, Nov 19 2009
User Panel: Can Formal Tools Reduce Need For Simulation?
It was not surprising that a customer Q&A panel at the Logic Design Technology Event, held at Cadence last week, would focus almost entirely on functional verification. As one panelist noted, verification consumes over 50 percent of the design effort. What I found interesting was the amount of discussion...
Posted to
Industry Insights
(Weblog)
by
rgoering
on Mon, Nov 16 2009
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